DDC112 Datasheet, PDF (9/24 Pages) Burr-Brown (TI) – Dual Current Input 20-Bit ANALOG-TO-DIGITAL CONVERTER

Determining the Integration Capacitor (C_F) Value
The value of the integrator’s feedback capacitor, the integra-
tion period, and the reference voltage determine the positive
full-scale (+FS) value of the DDC112. The approximate
positive full-scale value of the DDC112 is given by the
following equations:
Q_IN = I_IN • T_INT
Q_FS = (0.96) V_REF • C_F
I _FS
=
(0.96) V_REF
T_INT
•
C_F
or
C_F
=
I_FS • T_INT
(0.96) V_REF
The “0.96” factor allows the front end integraters to reach
full scale without having to completely swing to ground.
The negative full-scale (–FS) range is approximately 0.4%
of the positive full-scale range. For example, Range 5 has a
nominal +FS range of 250pC. The –FS range is then ap-
proximately –1pC. This relationship holds for external ca-
pacitors as well and is independent of V_REF (for V_REF within
the allowable range, see the Specification table).
Integration Capacitors
There are seven different capacitors available on chip for
each side of each channel in the DDC112. These internal
capacitors are trimmed in production to achieve the speci-
fied performance for range error of the DDC112. The range
control pins (RANGE0-RANGE2) change the capacitor
value for all four integrators. Consequently, both inputs and
both sides of each input will always have the same full scale
range unless external capacitors are used.
External integration capacitors may be used instead of the
internal capacitors values by setting RANGE2-RANGE0
= 000. The external capacitor pin connections are sum-
marized in Table II. Usually, all four external capacitors
are equal in value, however, it is possible to have differ-
ing pairs of external capacitors between Input 1 and
Input 2 of the DDC112. Regardless of the selected value
of the capacitor, it is strongly recommended that the
capacitors for sides A and B be the same.
EXTERNAL CAPACITOR PINS
ON THE DDC112
INTEGRATOR
Channel
Side
5 and 6
3 and 4
23 and 24
25 and 26
1
A
1
B
2
A
2
B
TABLE II. External Capacitor Connections with Range Con-
figuration of RANGE2-RANGE0 = 000.
Since the range accuracy depends on the characteristics of
the integration capacitor, they must be carefully selected. An
external integration capacitor should have low voltage coef-
ficient, temperature coefficient, memory, and leakage cur-
rent. The optimum selection depends on the requirements of
the specific application. Suitable types include COG ce-
ramic, polycarbonate, polystyrene, and silver mica.
Voltage Reference
The external voltage reference is used to reset the integration
capacitors before an integration cycle begins. It is also used
by the ∆Σ converter while the converter is measuring the
voltage stored on the integrators after an integration cycle
ends. During this sampling, the external reference must
supply charge needed by the ∆Σ converter. For an integra-
tion time of 500µs, this charge translates to an average V_REF
current of approximately 150µA. The amount of charge
needed by the ∆Σ converter is independent of the integration
time, therefore, increasing the integration time lowers the
average current. For example, an integration time of 1000µs
lowers to average V_REF current to 75µA.
It is critical that V_REF be stable during the different modes of
operation shown in Figure 5. The ∆Σ converter measures the
voltage on the integrator with respect to V_REF. Since the
integrator’s capacitors are initially reset to V_REF, any droop
in V_REF from the time the capacitors are reset to the time
when the converter measures the integrator’s output will
introduce an offset. It is also important that V_REF be stable
over longer periods of time as changes in V_REF correspond
directly to changes in the full-scale range. Finally, V_REF
should introduce as little additional noise as possible.
For reasons mentioned above, it is strongly recommended
that the external reference source be buffered with an
operational amplifier, as shown in Figure 6. In this circuit,
the voltage reference is generated by a 4.096V reference.
+5V
4.99kΩ
10kΩ
1
LM404-4.1
+
10µF
+5V
0.10µF
7
2
6
OPA350
3
0.10µF
4
+
10µF
0.1µF
To V_REF
Pin 22 of
the DDC112
FIGURE 6. Recommended External Voltage Reference Circuit for Best Low Noise Operation with the DDC112.
®
9
DDC112