DDC112 Datasheet, PDF (10/24 Pages) Burr-Brown (TI) – Dual Current Input 20-Bit ANALOG-TO-DIGITAL CONVERTER

A low-pass filter to reduce noise connects it to an opera-
tional amplifier configured as a buffer. This amplifier
should have a unity gain bandwidth greater than 4MHz,
low noise, and input/output common-mode ranges that
support V_REF. Following the buffer are capacitors placed
close to the DDC112’s V_REF pin. Even though the circuit in
Figure 6 might appear to be unstable due to the large output
capacitors, it works well for most operational amplifiers. It
is NOT recommended that series resistance be placed in the
output lead to improve stability since this can cause droop
in V_REF which produces large offsets.
0
–10
–20
–30
–40
–50
0.1
T_INT
1
T_INT
10
T_INT
100
T_INT
Frequency
FIGURE 7. Frequency Response of the DDC112.
DDC112 Frequency Response
The frequency response of the DDC112 is set by the front end
integrators and is that of a traditional continuous time integra-
tor, as shown in Figure 7. By adjusting T_INT, the user can
change the 3dB bandwidth and the location of the notches in
the response. The frequency response of the ∆Σ converter that
follows the front end integrator is of no consequence because
the converter samples a held signal from the integrators. That
is, the input to the ∆Σ converter is always a DC signal. Since
the output of the front end integrators are sampled, aliasing can
occur. Whenever the frequency of the input signal exceeds
one-half of the sampling rate, the signal will “fold” back down
to lower frequencies.
Test Mode
When TEST is used, pins IN1 and IN2 are grounded and
“packets” of approximately 13pC charge are transferred to
the integration capacitors of both Input 1 and Input 2. This
fixed charge can be transferred to the integration capacitors
either once during an integration cycle or multiple times. In
the case where multiple packets are transferred during one
integration period, the 13pC charge is additive. This mode
can be used in both the continuous and non-continuous
mode timing. The timing diagrams for test mode are shown
in Figure 8. The top three lines in Figure 8 define the timing
when one packet of 13pC is sent to the integration capaci-
tors. The bottom three lines define the timing when multiple
packets are sent to the integration capacitors.
Action
Test Mode Disabled
Integrate B Integrate A
13pC into B
Test Mode Enabled
13pC into A 13pC into B
13pC into A
Test Mode Disabled
Integrate B Integrate A
CONV
TEST
t₁
t₂
Test Mode Disabled
Action
Integrate B Integrate A
13pC into B
Test Mode Enabled
26pC into A 39pC into B
52pC into A
Test Mode Disabled
Integrate B Integrate A
CONV
TEST
t₄
t₅
t₁
t₃
FIGURE 8. Timing Diagram of the Test Mode of the DDC112.
CLK = 10MHz
SYMBOL
DESCRIPTION
MIN
TYP
MAX
t₁
Setup Time for Test Mode Enable
100
t₂
Setup Time for Test Mode Disable
100
t₃
Hold Time for Test Mode Enable
100
t₄
From Rising Edge of TEST to the Edge of CONV
5.4
while Test Mode Enabled
t₅
Rising Edge to Rising Edge of TEST
5.4
TABLE III. Timing for the DDC112 in the Test Mode.
®
DDC112
10
t₂
t₄
CLK = 15MHz
MIN
TYP
MAX
100
100
100
3.6
3.6
UNITS
ns
ns
ns
µs
µs