DDC112 Datasheet, PDF (13/24 Pages) Burr-Brown (TI) – Dual Current Input 20-Bit ANALOG-TO-DIGITAL CONVERTER

The time needed for the m/r/az cycle, t₆, is the same time that
determines the boundary between the cont and ncont modes
described earlier in the Overview section. DVALID goes
LOW after CONV toggles in time t₁, indicating that data is
ready to be retrieved. As shown in Figure 10, there are two
values for t₇, depending on T_INT. The reason for this will be
discussed in the Special Considerations section.
Figure 11 shows the result of inverting the logic level of
CONV. The only difference is in the first three states.
Afterwards, the states toggle between 4 and 5 just as in the
previous example. Figure 12 shows the timing diagram of
the internal operations occurring during continuous mode
operation.
CONV
State 8
7
Integration
Status
m/r/az
Status
mbsy
DVALID
t=0
Power-Up
6
Integrate B
5
Integrate A
m/r/az B
t₆
4
Integrate B
m/r/az A
5
Integrate A
m/r/az B
t₇
Side B
Data
Side A
Data
Side B
Data
FIGURE 11. Continuous Mode Timing (CONV LOW at power-up).
End Integration Side A
Start Integration Side B
End Integration Side B
Start Integration Side A
End Integration Side A
Start Integration Side B
CONV
T_INT
T_INT
A/D Conversion
Input 1 (Internal)
A/D Conversion
Input 2 (Internal)
DVALID
Side A
t₁₂
t₁₃
Side A
t₁₂
Side B
Side B
t₁₄
Side A
Data Ready
Side B
Data Ready
FIGURE 12. Timing Diagram of the Internal Operation in Continuous Mode of the DDC112.
Side A
SYMBOL
T_INT
t₁₂
t₁₃
t₁₄
DESCRIPTION
Integration Period (continuous mode)
A/D Conversion Time (internally controlled)
A/D Conversion Reset Time (internally controlled)
Integrator and A/D Conversion Reset Time
(internally controlled)
CLK = 10MHz
MIN
TYP
MAX
500
1,000,000
202.2
13.2
61.8
TABLE VI. Timing for the Internal Operation in the Continuous Mode.
CLK = 15MHz
MIN
TYP
MAX
333
1,000,000
134.66
8.8
41.2
13
DDC112
UNITS
µs
µs
µs
µs
®