DDC112 Datasheet, PDF (11/24 Pages) Burr-Brown (TI) – Dual Current Input 20-Bit ANALOG-TO-DIGITAL CONVERTER

TEST and CONV work together to implement this feature.
The test mode is entered when TEST is HIGH prior to a
CONV edge. At that point, a CONV edge triggers the
grounding of the analog inputs and the switching of 13pC
packets of charge onto the integration capacitors. If TEST is
kept HIGH through at least two conversions (i.e., a rise and
fall of CONV), all four integrators will be charged with a
13pC packet. At the end of each conversion, the voltage at
the output of the integrators is digitized as discussed in the
“Continuous Mode” and “Non-Continuous Mode” section
of this data sheet. The test mode is exited when TEST is
LOW and a CONV edge occurs.
Once the test mode is entered as described above, TEST can
cycle as many times as desired. When this is done, additional
13pC packets are added on the rising edge of TEST to the
existing charge on the integrator capacitors. Multiple charge
packets can be added in this way as long as the TEST pin is
not LOW when CONV toggles.
DIGITAL ISSUES
The digital interface of the DDC112 provides the digital
results via a synchronous serial interface consisting of a data
clock (DCLK), a transmit enable pin (DXMIT), a valid data
pin (DVALID), a serial data output pin (DOUT), and a serial
data input pin (DIN). The DDC112 contains only one A/D
converter, so the conversion process is interleaved between
the two inputs (see Figure 2). The integration and conversion
process is fundamentally independent of the data retrieval
process. Consequently, the CLK frequency and DCLK fre-
quencies need not be the same. DIN is used when multiple
converters are cascaded. Cascading or “daisy chaining”
greatly simplifies the interconnection and routing of the
digital outputs in cases where a large number of converters
are needed. Refer to “Cascading Multiple Converters” section
of this data sheet for more detail.
The conversion rate of the DDC112 is set by a combination
of the integration time (determined by the user) and the speed
of the A/D conversion process. The A/D conversion time is
primarily a function of the system clock (CLK) speed. One
A/D conversion cycle encompasses the conversion of two
signals (one from each input of the DDC112) and reset time
for each of the integrators involved in the two conversions. In
most situations, the A/D conversion time is shorter than the
integration time. If this condition exists, the DDC112 will
operate in the continuous mode. When the DDC112 is in the
continuous mode, the sensor output is continuously integrated
by one of the two sides of each input.
In the event that the A/D conversion takes longer than the
integration time, the DDC112 will switch into a non-con-
tinuous mode. In non-continuous mode, the A/D converter is
not able to keep pace with the speed of the integration
process. Consequently, the integration process is periodi-
cally halted until the digitizing process catches up. These
two basic modes of operation for the DDC112—continuous
and non-continuous modes—are described below.
Continuous and Non-Continuous
Operational Modes
The state diagram of the DDC112 is shown in Figure 9. In
all, there are 8 states. Table IV provides a brief explanation
of each of the states.
STATE
1
MODE
Ncont
2
Ncont
3
Cont
4
Cont
5
Cont
6
Cont
7
Ncont
8
Ncont
DESCRIPTION
Complete m/r/az of side A, then side B (if previous
state is state 4). Initial power-up state when CONV
is initially held HIGH.
Prepare side A for integration.
Integrate on side A.
Integrate on side B; m/r/az on side A.
Integrate on side A; m/r/az on side B.
Integrate on side B.
Prepare side B for integration.
Complete m/r/az of side B, then side A (if previous
state is state 5). Initial power-up state when CONV
is initially held LOW.
TABLE IV. State Descriptions.
mbsy
1
Ncont
CONV • mbsy
2
Ncont
CONV • mbsy
CONV
4
Int B/Meas A
Cont
3
Int A
Cont
CONV
CONV • mbsy
CONV • mbsy
5
Int A/Meas B
Cont
CONV
7
Ncont
6
Int B
Cont
CONV
CONV • mbsy
CONV • mbsy
8
Ncont
mbsy
FIGURE 9. State Diagram.
Four signals are used to control progression around the state
diagram: CONV and mbsy and their complements. The state
machine uses the level as opposed to the edges of CONV to
control the progression. mbsy is an internally generated
signal not available to the user. It is active whenever a
measurement/reset/auto-zero (m/r/az) cycle is in progress.
®
11
DDC112