CS4235 Datasheet, PDF (86/94 Pages) Cirrus Logic – CrystalClear Low Cost ISA Audio System

CS4235
CrystalClear ^TM Low Cost ISA Audio System
SDATA - Wavetable Serial Audio Data, Input
This input supplies the serial audio PCM data to be mixed to the stereo DAC2 of the CS4235.
The data consists of left and right channel 16-bit data delineated by LRCLK. This pin should be
connected to the SOUT output pin on the CS9236. This pin should also have a weak pull-down
resistor of approx. 100 kΩ to minimize power-down currents and allow for stuffing options.
LRCLK - Wavetable Serial Left/Right Clock, Input
This input supplies the serial data alignment signal that delineates left from right data. This pin
should be connected to the LRCLK output pin on the CS9236. This pin should also have a
weak pull-down resistor of approx. 100 kΩ to minimize power-down currents and allow for
stuffing options.
MCLK - Wavetable Master Clock, Output (CDROM enable)
This output supplies the 16.9344 MHz master clock that controls all the timing on the CS9236.
This pin should be connected to the MCLK5I input pin on the CS9236. MCLK can be disabled
in software using the DMCLK bit in C8 in the Control logical device space. DMCLK provides
a partial software power-down mode for the CS9236. At power-up, this pin is an input (with an
internal 100 kΩ pullup) that, when pulled low with a 10 kΩ resistor to SGND, enables the
CDROM interface (over the upper four ISA address pins).
CDROM Interface
The four CDROM pins are multi-function and default to ISA upper address bits SA12-SA15.
To enable the CDROM port, an external 10 kΩ resistor must be tied between MCLK and
SGND. MCLK is sampled on the falling edge of RESDRV. The alternate CDROM chip select
has its own strapping option to enable ACDCS. Use of the CDROM interface requires a 1 k
E²PROM to support the Plug-and-Play data as well as firmware patch data.
CDCS - CDROM Chip Select, Output, 4 mA drive
This output goes low whenever an address is decoded that matches the value programmed into
the CDROM base address register.
ACDCS - Alternate CDROM Chip Select, Output, 4 mA drive
This pin, XCTL1/ACDCS/DOWN, is multiplexed with two other functions, and defaults to the
XCTL1 output which is controlled by the XCTL1 bit in the WSS I10. This pin can also be
configured at a second CDROM Chip Select, ACDCS, to support the alternate IDE CDROM
decode. To force this pin to the CDROM alternate chip select, an external 10 kΩ resistor must
be tied between SDOUT and SGND. ACDCS output then goes low whenever an address is
decoded that matches the value programmed into the CDROM alternate base address register,
ACDbase. This pin can also be used as the volume up pin DOWN by setting VCEN in Control
register C0 or the Hardware Configuration data. VCEN has the highest precedence over the
other pin functions.
86
DS252PP2