CS4235 Datasheet, PDF (31/94 Pages) Cirrus Logic – CrystalClear Low Cost ISA Audio System

CS4235
CrystalClear ^TM Low Cost ISA Audio System
Status Register
(WSSbase+2, R2, Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
CU/L CL/R CRDY SER PU/L PL/R PRDY INT
INT
Interrupt Status: This indicates the
status of the internal interrupt logic
of the WSS Codec. This bit is
cleared by any write of any value to
this register. The IEN bit of the Pin
Control register (I10) determines
whether the state of this bit is re-
flected on the IRQ pin assigned to
the WSS Codec.
Read States
0 - Interrupt inactive
1 - Interrupt active
PRDY
Playback Data Ready. The Playback
Data register (R3) is ready for more
data. This bit would be used when di-
rect programmed I/O data transfers
are desired.
0 - Data still valid. Do not overwrite.
1 - Data stale. Ready for next host
data write value.
PL/R
Playback Left/Right Sample: This bit
indicates whether data needed is for
the Left channel or Right channel.
0 - Right needed
1 - Left or Mono needed
PU/L
Playback Upper/Lower Byte: This bit
indicates whether the playback data
needed is for the upper or lower
byte of the channel.
0 - Lower needed
1 - Upper or 8-bit needed
SER
Sample Error: This bit indicates that a
sample was not serviced in time and
an error has occurred. The bit indi-
cates an overrun for capture and
underrun for playback. If both the
capture and playback are enabled,
the source which set this bit can not
DS252PP2
be determined. However, the Alter-
nate Feature Status register (I24)
indicates the exact source of error.
CRDY
Capture Data Ready. The Capture
Data register (R3) contains data
ready for reading by the host. This
bit would be used for direct pro-
grammed I/O data transfers.
0 - Data is stale. Do not reread the
information.
1 - Data is fresh. Ready for next
host data read.
CL/R
Capture Left/Right Sample: This bit
indicates whether the capture data
waiting is for the Left channel or
Right channel.
0 - Right
1 - Left or Mono
CU/L
Capture Upper/Lower Byte: This bit
indicates whether the capture data
ready is for the upper or lower byte
of the channel.
0 - Lower available
1 - Upper or 8-bit available
Note on PRDY/CRDY: These two bits are de-
signed to be read as one when action is required
by the host. For example, when PRDY is set to
one, the device is ready for more data; or when
the CRDY is set to one, data is available to the
host. The definition of the CRDY and PRDY bits
are therefore consistent in this regard.
I/O DATA REGISTERS
The PIO Data register is two registers mapped to
the same address. Writes to this register sends
data to the Playback Data register. Reads from
this register will receive data from the Capture
Data register.
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