CS4235 Datasheet, PDF (39/94 Pages) Cirrus Logic – CrystalClear Low Cost ISA Audio System

CS4235
CrystalClear ^TM Low Cost ISA Audio System
Playback Upper Base (I14)
Default = 00000000
D7 D6 D5 D4 D3 D2 D1 D0
PUB7 PUB6 PUB5 PUB4 PUB3 PUB2 PUB1 PUB0
PUB7-PUB0
Playback Upper Base: This register is
the upper byte which represents the
8 most significant bits of the 16-bit
Playback Base register. Reads from
this register return the same value
which was written. The Current
Count registers cannot be read.
When set for MODE 1 or SDC, this
register is used for both the Play-
back and Capture Base registers.
Playback Lower Base (I15)
Default = 00000000
D7 D6 D5 D4 D3 D2 D1 D0
PLB7 PLB6 PLB5 PLB4 PLB3 PLB2 PLB1 PLB0
PLB7-PLB0
Lower Base Bits: This register is the
lower byte which represents the 8
least significant bits of the 16-bit
Playback Base register. Reads from
this register return the same value
which was written. When set for
MODE 1 or SDC, this register is
used for both the Playback and Cap-
ture Base registers.
Alternate Feature Enable I (I16)
Default = 0000eee0
D7 D6 D5 D4 D3 D2
rbc res CMCE PMCE SF1 SF0
D1 D0
SPE DACZ
DACZ
DAC Zero: This bit will force the out-
put of the playback channel to AC
zero when an underrun error occurs
1 - Go to center scale
0 - Hold previous valid sample
SPE
DSP Serial Port Enable. When
set, audio data from the ADCs is
sent out SDOUT and audio data
SF1,SF0
PMCE
CMCE
from SDIN is sent to the DACs.
MCE in R0 must be set to change
this bit. This bit is initialized through
the Hardware Configuration data.
1 - Enable serial port
0 - Disable serial port.
DSP Serial Format. Selects the
format of the serial port when en-
abled by SPE. MCE in R0 must be
set to change these bits. These bits
are initialized through the Hardware
Configuration data.
0 - 64-bit enhanced. Figure 6.
1 - 64-bit. Figure 7.
2 - 32-bit. Figure 8.
3 - ADC/DAC. Figure 9.
Playback Mode Change Enable.
When set, it allows modification of
the stereo/mono and audio data for-
mat bits (D7-D4) for the playback
channel, I8. MCE in R0 must be
used to change the sample fre-
quency.
Capture Mode Change Enable.
When set, it allows modification of
the stereo/mono and audio data for-
mat bits (D7-D4) for the capture
channel, I28. MCE in R0 must be
used to change the sample fre-
quency in I8.
Alternate Feature Enable II (I17)
Default = 0000x000
D7 D6 D5 D4 D3 D2 D1 D0
TEST TEST TEST TEST rbc res rbc HPF
HPF
TEST
High Pass Filter: This bit enables a
DC-blocking high-pass filter in the
digital filter of the ADC. This filter
forces the ADC offset to 0.
0 - disabled
1 - enabled
Factory Test. These bits are used for
factory testing and must remain at 0
for normal operation.
DS252PP2
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