CS4235 Datasheet, PDF (73/94 Pages) Cirrus Logic – CrystalClear Low Cost ISA Audio System

CS4235
CrystalClear ^TM Low Cost ISA Audio System
The two formats listed above as illustrated in
Figure 17.
Up
Down
Mute
GND
VCF1 = 0
Up
Down
Mute
GND
VCF1 = 1
Figure 17. Volume Control Formats
Crystal / Clock
Two pins have been allocated to allow the inter-
facing of a crystal oscillator: XTALI and
XTALO. The crystal should be designed as fun-
damental mode, parallel resonant, with a load
capacitor of between 10 and 20 pF. The capaci-
tors connected to each of the crystal pins should
be twice the load capacitance specified to the
crystal manufacturer.
An external CMOS clock may be connected to
the crystal input XTALI in lieu of the crystal.
When using an external CMOS clock, the
XTALO pin must be left floating with no trace
or external connection of any kind.
General Purpose Output Pins
Two general purpose outputs are provided to en-
able control of external circuitry (i.e. mute
function). XCTL1 and XCTL0 in the WSS
Codec register I10 are output directly to the ap-
propriate pin when enabled.
Pin XCTL1/ACDCS/DOWN is initially control-
led by the VCEN bit in the Hardware
Configuration data. If VCEN is zero, this pin be-
comes XCTL1 if the SDOUT pin is sampled
high during a high-to-low transition of RESDRV.
This pin can also output ACDCS if the SDOUT
pin is sampled low during a high-to-low transi-
tion of the RESDRV pin. SDOUT has an internal
DS252PP2
pullup resistor. VCEN has the highest prece-
dence and will cause this pin to convert to the
DOWN function whenever VCEN is set.
Reset and Power Down
A RESDRV pin places the part into maximum
power conservation mode. When RESDRV goes
high, the PnP registers are reset - all logical de-
vices are disabled, all analog outputs are muted,
and the voltage reference then slowly decays to
ground. When RESDRV is brought low, an in-
itialization procedure begins which causes a full
calibration cycle to occur. When initialization is
completed, the registers will contain their reset
value and the part will be isolated from the bus.
RESDRV is required whenever the part is pow-
ered up. The initialization time varies based on
whether an E²PROM is present or not and the
size of the data in the E²PROM. After RESDRV
goes low, the part should not be written to for
approximately 200 ms to guarantee that the part
is ready to respond to commands. The exact tim-
ing is specified in the Timing Section in the front
of this data sheet.
Software low-power states are available through
bits in the Control or WSS logical device regis-
ter space. See the CONTROL INTERFACE
section for more information.
Address Port Configuration
The part provides a method for motherboards to
hide the part from standard PnP (or traditional
Crystal Key) software. BIOSes can use this
method to set the part at a unique address, and
report the device as a System Dev. Node to the
operating system.
On the high to low transition of the RESDRV
pin, the part samples the state of the APSEL and
SCL, which have internal 100 kΩ pullups to
+5 V. APSEL selects the Address Port used to
configure the part. When APSEL is left high, the
Address Port is 0x279 and backwards compat-
ible to previous chips and standard PnP software.
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