CS4235 Datasheet, PDF (59/94 Pages) Cirrus Logic – CrystalClear Low Cost ISA Audio System

CS4235
CrystalClear ^TM Low Cost ISA Audio System
RAM Access End
CTRLbase+6
D7 D6 D5 D4 D3 D2 D1 D0
RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0
RE7-RE0
A 0 written to this location resets the
previous location, CTRLbase+5,
from data download mode to com-
mand mode.
Global Status
CTRLbase+7, Default = 0000000x
D7 D6 D5 D4 D3 D2 D1 D0
CWSS ICTRL ISB IWSS IMPU WDT IMV res
IMV
WDT
Hardware Master Volume Control
Interrupt Status. When set, hard-
ware volume has changed. IMV is
cleared by reading this status regis-
ter. Master Volume Interrupts are
enabled through VCIE in C8.
Watch-Dog Timer. If an error occurs
on the ISA bus, the Processor will
be reset and WDT will be set.
IMPU
MPU-401 Interrupt status. MPU inter-
rupt pending when set to 1.
IWSS
Windows Sound System Interrupt
Status. WSS interrupt pending when
set to 1.
ISB
ICTRL
CWSS
Sound Blaster Interrupt status. Sound
Blaster interrupt pending when set to
1.
Control Logical Device 2 Interrupt
status. A context switch interrupt is
pending when set to 1.
Context - WSS. Indicates the current
context.
0 - Sound Blaster Emulation
1 - Windows Sound System
Control Indirect Registers
The Control Indirect registers are accessed
through CTRLbase+3 and CTRLbase+4.
CTRLbase+3 is the address register and
CTRLbase+4 is the data register used to access
C0 through C9 indirect registers.
Address
CTRLbase+3
CTRLbase+4
Register Name
Control Indirect Address
Control Indirect Data
Table 17. Control Indirect Access Registers
Index
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
Register Name
Reserved
Version / Chip ID
3D Space Control
3D Enable
Reserved
Reserved
Reserved
Reserved
Wavetable & Volume Control
Power Management
Table 18. Control Indirect Registers
DS252PP2
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