CS4235 Datasheet, PDF (63/94 Pages) Cirrus Logic – CrystalClear Low Cost ISA Audio System

CS4235
CrystalClear ^TM Low Cost ISA Audio System
MIDI UART
The UART is used to convert parallel data to the
serial data required by MIDI. The serial data rate
is fixed at 31.25 k baud (±1%). The serial data
format is RS-232 like: 1 start bit, 8 data bits, and
1 stop bit.
In multimedia systems, the MIDI pins are typi-
cally connected to the joystick connector as
illustrated in Figure 5.
MPU-401 "UART" Mode Operation
After power-up reset, the interface is in "non-
UART" mode. Non-UART mode operation is
defined as follows:
1. All writes to the Transmit Port, MPUbase+0,
are ignored.
2. All reads of the Receive Port, MPUbase+0,
return the last received buffer data.
3. All writes to the Command Port, MPUbase+1,
are monitored and acknowledged as follows:
a. A write of 3Fh sets the interface into
UART operating mode. An acknowledge
is generated by putting an FEh into the
receive buffer FIFO which generates an
interrupt.
b. A write of A0-A7, ABh, ACh, ADh, AFh
places an FEh into the receive buffer
FIFO (which generates an interrupt) fol-
lowed by a one byte write to the receive
buffer FIFO of 00h for A0-A7, and ABh
commands, 15h for ACh, 01h for ADh,
and 64h for AFh commands.
c. All other writes to the Command Port are
ignored and an acknowledge is gener-
ated by putting an FEh into the receive
buffer FIFO which generates an interrupt.
UART mode operation is defined as follows:
1. All writes to the Transmit Port, MPUbase+0,
are placed in the transmit buffer FIFO.
Whenever the transmit buffer FIFO is not
empty, the next byte is read from the buffer
and sent out the MIDOUT pin. The Status
Register, MPUbase+1, bit 6, TXS is updated
to reflect the transmit buffer FIFO status.
2. All reads of the Receive Port, MPUbase+0,
return the next byte in the receive buffer
FIFO. When serial data is received from the
MIDIN pin, it is placed in the next receive
buffer FIFO location. If the buffer is full,
the last location is overwritten with the new
data. The Status Register, MPUbase+1,
bit 7, RXS is updated to reflect the new re-
ceive buffer FIFO state.
3. A write to the Command Register,
MPUbase+1, of FFh will return the interface
to non-UART mode.
4. All other writes to the Command Register,
MPUbase+1, are ignored.
FM SYNTHESIZER
A games-compatible internal FM synthesizer is
included which responds to both the SBPro FM
synthesis addresses as well as the SYNbase ad-
dresses.
To enable the internal FM synthesis engine, the
IFM bit in the Hardware Configuration data,
byte 8 (Global Configuration Byte) must be set.
This bit is also available in WSS register X4.
Volume control for the internal FM synthesizer is
supported through I18 and I19 in the WSS ex-
tended register space.
The synthesizer interface is compatible with the
Adlib and Sound Blaster standards. The typical
Adlib I/O address is SYNbase = 388h.
DS252PP2
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