CS4235 Datasheet, PDF (58/94 Pages) Cirrus Logic – CrystalClear Low Cost ISA Audio System

CS4235
CrystalClear ^TM Low Cost ISA Audio System
Block Power Down
CTRLbase+2, Default = 00000000
D7 D6 D5 D4 D3 D2 D1 D0
PDWN SRC VREF MIX ADC1 DAC1 PROC FM
FM
Internal FM synthesizer powered
down when set.
PROC
Processor set to idle mode. When set,
places the internal processor in an
idle state. This effects the PnP inter-
face, MPU401, and SBPro devices.
Any command to any one of these
interfaces will cause the processor
to go active.
DAC1
DAC1 power down. When set, powers
down DAC1. Playback is disabled.
ADC1
ADC1 power down. When set, powers
down the ADC1. Capture is disabled.
MIX
Mixer power down. All analog input
and output channels are powered
down. All outputs are centered
around VREF if the VREF bit is set.
A reset is not required to maintain
the calibrated state if the mixer is
powered down but the VREF bit is
not set.
VREF
VREF power down. When set, powers
down the entire mixer. Since
powering down VREF, powers down
the entire analog section, some audi-
ble pops can occur.
SRC
Internal Sample-Rate Converters are
powered down. Only 44.1 kHz sam-
ple frequency is allowed when this
bit is set.
PDWN
Global Power Down with data reten-
tion. When set, the entire chip is
powered down, except reads and
writes to this register. When this bit
is cleared, a full calibration is initi-
ated. All registers retain their values;
therefore, normal operation can re-
sume after calibration is completed.
58
NOTE: Software should mute the DACs and Mixers
and FM volume when asserting any power-down
modes to prevent clicks and pops.
Control Indirect Address Register
CTRLbase+3
D7 D6 D5 D4 D3 D2 D1 D0
res res res res CA3 CA2 CA1 CA0
CA3-CA0
Address bits to access the Control
Indirect registers C0-C9 through
CTRLbase+4
Control Indirect Data Register
CTRLbase+4
D7 D6 D5 D4 D3 D2 D1 D0
CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0
CD7-CD0
Control Indirect Data register. This
register provides access to the indi-
rect registers C0-C9, where
CTRLbase+3 selects the actual reg-
ister. See the Control Indirect
Register section for more details.
Control/RAM Access
CTRLbase+5
D7 D6 D5 D4 D3 D2 D1 D0
CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0
CR7-CR0
This register controls the loading of
the part’s internal RAM. RAM sup-
port includes hardware configuration
and PnP default resource data, as
well as program memory. See the
Hostload Procedure section for more
information. Commands are followed
by address and data information.
Commands: 0x55 - Disable PnP Key
0x56 - Disable Crystal Key
0x53 - Disable Crystal Key 2
0x5A - Update Hardware Configura-
tion Data.
0xAA - Download RAM. Address
followed by data. (Stopped by writ-
ing 0 to CTRLbase+6)
DS252PP2