CS4235 Datasheet, PDF (14/94 Pages) Cirrus Logic – CrystalClear Low Cost ISA Audio System

CS4235
CrystalClear ^TM Low Cost ISA Audio System
ISA Bus
SA12
SA13
SA14
SA15
AEN
+5V
74ALS138
1
A
2
B
15
Y0
Y1
3
C
Y2
Y3
Y4
4 _{G2A Y5}
5 _{G2B Y6}
6 _{G1 Y7}
AEN
Figure 2. 16-bit Decode Circuit
DMA CYCLES
The part supports up to three 8-bit ISA-compat-
ible DMA channels. The default hardware
connections, which can be changed through the
hardware configuration data, are:
DMA A = ISA DMA channel 0
DMA B = ISA DMA channel 1
DMA C = ISA DMA channel 3
The typical configuration would require two
DMA channels. One for the WSS Codec and
Sound Blaster playback, and the other for WSS
Codec capture (to support full-duplex). The
CDROM, if used, can also support a DMA chan-
nel, although this is not typical.
DMA cycles are distinguished from control reg-
ister cycles by the generation of a DRQ (DMA
Request). The host acknowledges the request by
generating a DACK (DMA Acknowledge) sig-
nal. The transfer of audio data occurs during the
DACK cycle. During the DACK cycle the ad-
dress lines are ignored.
The digital audio data interface uses DMA re-
quest/grant pins to transfer the digital audio data
between the part and the ISA bus. Upon receipt
of a DMA request, the host processor responds
with an acknowledge signal and a command
strobe which transfers data to and from the part,
14
eight bits at a time. The request pin stays active
until the appropriate number of 8-bit cycles have
occurred. The number of 8-bit transfers will vary
depending on the digital audio data format, bit
resolution, and operation mode.
The DMA request signal can be asserted at any
time. Once asserted, the DMA request will re-
main asserted until a complete DMA cycle
occurs. A complete DMA cycle consists of one
or more bytes depending on which device inter-
nal to the part is generating the request.
INTERRUPTS
For Plug-and-Play flexibility, seven interrupt
pins are supported, although only one or two are
typically used. The default hardware connec-
tions, which can be modified through the
hardware configuration data, are:
IRQ A = ISA Interrupt 5
IRQ B = ISA Interrupt 7
IRQ C = ISA Interrupt 9
IRQ D = ISA Interrupt 11
IRQ E = ISA Interrupt 12
IRQ F = ISA Interrupt 15
IRQ G is new and defaults to not being con-
nected for backwards compatibility. This new
interrupt pin would typically be connected to
ISA Interrupt 10. New designs that use IRQ G
must change the Hardware Configuration Data to
indicate which ISA Interrupt is connected to
IRQ G.
The typical configuration would support two in-
terrupt sources: one shared between the WSS
Codec and the Sound Blaster Pro compatible de-
vices, and the other for the MPU401 device.
Interrupts are also supported for the FM Synthe-
sizer, Control, and CDROM devices, but are
typically not used.
DS252PP2