AT24C01D_14 Datasheet, PDF (9/26 Pages) ATMEL Corporation – IC-Compatible (2-wire) Serial EEPROM

Figure 5-2. Page Write
SCL
12 3 4 567 89 12 345 67 89
SDA
Start
by
Master
Device Address Byte
Word Address Byte
1 0 1 0 A₂ A₁ A₀ 0 0 A7 A6 A5 A4 A3 A2 A1 A0 0
MSB
MSB
ACK
from
Slave
ACK
from
Slave
12 3 4 567 89 12 345 67 89
Data Word (n)
Data Word (n+x), max of 8 without rollover
D7 D6 D5 D4 D3 D2 D1 D0 0 D7 D6 D5 D4 D3 D2 D1 D0 0
MSB
MSB
ACK
from
Slave
ACK
from
Slave
Stop
by
Master
5.3 Acknowledge Polling
An Acknowledge Polling routine can be implemented to optimize time sensitive applications that would prefer not to
wait the fixed maximum write cycle time (t_WR). This method allows the application to know immediately when the
Serial EEPROM write cycle has completed, so a subsequent operation can be started.
Once the internally self-timed write cycle has started, an Acknowledge Polling routine can be initiated. This
involves repeatedly sending a Start condition followed by a valid Device Address byte with the R/W bit set at
Logic 0. The device will not respond with an ACK while the write cycle is ongoing. Once the internal write cycle has
completed, the EEPROM will respond with an ACK, allowing a new Read or Write operation to be immediately
initiated. A flow chart has been included below in Figure 5-3 to better illustrate this technique.
Figure 5-3. Acknowledge Polling Flow Chart
Send any
Write
protocol
Send
Stop
condition
to initiate the
write cycle
Send Start
condition followed
by a valid
Device Address
byte with R/W = 0
Did
the device
ACK?
YES
Proceed to
next Read or
Write operation
NO
AT24C01D and AT24C02D [DATASHEET]
9
Atmel-8871B-SEEPROM-AT24C01D-02D-Datasheet_032014