AT24C01D_14 Datasheet, PDF (2/26 Pages) ATMEL Corporation – IC-Compatible (2-wire) Serial EEPROM

1. Pin Descriptions and Pinouts
Table 1-1. Pin Descriptions
Pin
Number
1, 2, 3
4
5
6
7
8
Pin
Symbol
A₀, A₁, A₂
GND
SDA
SCL
WP
V_CC
Pin Name and Functional Description
Device Address Inputs: The A₀, A₁, and A₂ pins are used to select the
hardware device address and correspond to the seventh, sixth, and fifth bit
of the I²C seven bit slave address. These pins can be directly connected to
V_CC or GND, allowing up to eight devices on the same bus.
Refer to Note 1 for behavior of the pin when not connected.
Ground: The ground reference for the power supply. GND should be
connected to the system ground.
Serial Data: The SDA pin is an open-drain bidirectional input/output pin
used to serially transfer data to and from the device.
The SDA pin must be pulled-high using an external pull-up resistor (not to
exceed 10K in value) and may be wire-ORed with any number of other
open-drain or open-collector pins from other devices on the same bus.
Serial Clock: The SCL pin is used to provide a clock to the device and to
control the flow of data to and from the device. Command and input data
present on the SDA pin is always latched in on the rising edge of SCL,
while output data on the SDA pin is clocked out on the falling edge of SCL.
The SCL pin must either be forced high when the serial bus is idle or
pulled-high using an external pull-up resistor.
Write Protect: Connecting the WP pin to GND will ensure normal write
operations.When the WP pin is connected to VCC, all write operations to
the memory are inhibited.
Refer to Note 1 for behavior of the pin when not connected.
Device Power Supply: The V_CC pin is used to supply the source voltage to
the device. Operations at invalid V_CC voltages may produce spurious
results and should not be attempted.
Asserted
State
—
—
—
—
High
—
Pin
Type
Input
Power
Input/
Output
Input
Input
Power
Note:
1. If the A₀, A₁, A₂, or WP pins are not driven, they are internally pulled down to GND. In order to operate in a wide
variety of application environments, the pull-down mechanism is intentionally designed to be somewhat strong.
Once these pins are biased above the CMOS input buffer’s trip point (~0.5 x V_CC), the pull-down mechanism
disengages. Atmel recommends connecting these pins to a known state whenever possible.
8-lead SOIC
A₀
A₁
A₂
GND
1
8
2
7
3
6
4
5
Top View
V_CC
WP
SCL
SDA
8-lead TSSOP
A₀
1
8
A₁
2
7
A₂
GND
3
4
6
5
Top View
8-pad UDFN
V_CC
WP
SCL
SDA
A₀ 1
A₁ 2
A₂ 3
GND 4
8 V_CC
7 WP
6 SCL
5 SDA
Top View
8-lead PDIP
A₀ 1
A₁ 2
A₂ 3
GND 4
8 V_CC
7 WP
6 SCL
5 SDA
Top View
(1)
5-lead SOT23
SCL 1 5 WP
GND 2
SDA
34
V_CC
Top View
8-ball VFBGA
A₀ 1
A₁ 2
A₂ 3
GND 4
8 V_CC
7 WP
6 SCL
5 SDA
Top View
Note: Package drawings are not to scale
Note: 1. Refer to “Device Addressing” on page 7 for details about addressing the SOT23 version of the device.
2
AT24C01D and AT24C02D [DATASHEET]
Atmel-8871B-SEEPROM-AT24C01D-02D-Datasheet_032014