AT24C01D_14 Datasheet, PDF (11/26 Pages) ATMEL Corporation – IC-Compatible (2-wire) Serial EEPROM

6. Read Operations
Read operations are initiated the same way as Write operations with the exception the read/write select bit in the
Device Address word must be a Logic 1. There are three Read operations:
 Current Address Read
 Random Address Read
 Sequential Read
6.1 Current Address Read
The internal data word address counter maintains the last address accessed during the last Read or Write
operation, incremented by one. This address stays valid between operations as long as the V_CC is maintained to
the part. The address roll-over during read is from the last byte of the last page to the first byte of the first page of
the memory.
A Current Address Read operation will output data according to the location of the internal data word address
counter. This is initiated with a Start condition, followed by a valid Device Address byte with the R/W bit set to
Logic 1. The device will ACK this sequence and the current address data word is serially clocked out on the SDA
line. All types of Read operations will be terminated if the bus Master does not respond with an ACK (it NACKs)
during the ninth clock cycle. A Read instruction may be terminated at any point with a Stop condition which will
force the device into standby mode.
Figure 6-1. Current Address Read
SCL
12 3 4 567 89 12 345 67 89
SDA
Start
by
Master
Device Address Byte
Data Word (n)
1 0 1 0 A₂ A₁ A₀ 1 0 D7 D6 D5 D4 D3 D2 D1 D0 1
MSB
MSB
ACK
from
Slave
NACK
from
Master
Stop
by
Master
6.2 Random Read
A Random Read begins in the same way as a Byte Write operation does to load in a new data word address. This
is known as a “dummy write” sequence. However, the Data Byte and the Stop condition of the Byte Write must be
omitted to prevent the part from entering an internal write cycle. Once the Device Address and Word Address are
clocked in and acknowledged by the EEPROM, the bus Master must generate another Start condition. The bus
Master now initiates a Current Address Read by sending a Start condition, followed by a valid Device Address byte
with the R/W bit set to Logic 1. The EEPROM will ACK the Device Address and serially clock out the data word on
the SDA line. All types of Read operations will be terminated if the bus Master does not respond with an ACK (it
NACKs) during the ninth clock cycle. A Read instruction may be terminated at any point with a Stop condition
which will force the device into standby mode.
AT24C01D and AT24C02D [DATASHEET] 11
Atmel-8871B-SEEPROM-AT24C01D-02D-Datasheet_032014