AT24C01D_14 Datasheet, PDF (8/26 Pages) ATMEL Corporation – IC-Compatible (2-wire) Serial EEPROM

5. Write Operations
All Write operations for the AT24C01D/02D begin with the Master sending a Start condition, followed by a Device
Address byte with the R/W bit set to ‘0’, and then by the Word Address byte. The data value(s) to be written to the
device immediately follow the Word Address byte.
5.1 Byte Write
The AT24C01D/02D supports the writing of single 8-bit bytes. Selecting a data word in the 1-Kbit memory requires
a 7-bit word address while selecting a data word in the 2-Kbit memory requires an 8-bit word address.
Upon receipt of the proper Device Address and Word Address bytes, the EEPROM will send an Acknowledge. The
device will then be ready to receive the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM
will respond with an Acknowledge. The addressing device, such as a bus Master, must then terminate the Write
operation with a Stop condition. At that time the EEPROM will enter an internally self-timed write cycle, which will
complete within a time of t_WR, while the data is being programmed into the nonvolatile EEPROM. All inputs are
disabled during this write cycle, and the EEPROM will not respond until the Write is complete.
Figure 5-1. Byte Write
SCL
12 3 4 567 8912 3 4 567 89 12 3 4 567 89
Device Address Byte
Word Address Byte
Data Word
SDA
Start
by
Master
1 0 1 0 A₂ A₁ A₀ 0 0 A7 A6 A5 A4 A3 A2 A1 A0 0 D7 D6 D5 D4 D3 D2 D1 D0 0
MSB
MSB
MSB
ACK
from
Slave
ACK
from
Slave
ACK
from
Slave
Stop
by
Master
5.2 Page Write
A Page Write operation allows up to eight bytes to be written in the same write cycle, provided all bytes are in the
same row of the memory array (where address bits A7 through A3 are the same). Partial Page Writes of less than
eight bytes are also allowed.
A Page Write is initiated the same way as a Byte Write, but the bus Master does not send a Stop condition after the
first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the bus
Master can transmit up to seven additional data words. The EEPROM will respond with an ACK after each data
word is received. Once all data to be written has been sent to the device, the bus Master must issue a Stop
condition (see Figure 5-2) at which time the internally self-timed write cycle will begin.
The lower three bits of the word address are internally incremented following the receipt of each data word. The
higher order address bits are not incremented and retains the memory page row location. Page Write operations
are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written.
When the incremented word address reaches the page boundary, the address counter will “roll-over” to the
beginning of the same page. Nevertheless, creating a roll-over event should be avoided as previously loaded data
in the page could become unintentionally altered.
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AT24C01D and AT24C02D [DATASHEET]
Atmel-8871B-SEEPROM-AT24C01D-02D-Datasheet_032014