AT24C01D_14 Datasheet, PDF (15/26 Pages) ATMEL Corporation – IC-Compatible (2-wire) Serial EEPROM

8.5 Pin Capacitance⁽¹⁾
Applicable over recommended operating range from T_A = 25C, f = 1.0MHz, V_CC = 3.6V
Symbol Test Condition
Max
Units
C_I/O
Input/Output Capacitance (SDA)
8
pF
C_IN
Input Capacitance (A₀, A₁, A₂, SCL)
6
pF
Note: 1. This parameter is characterized but is not 100% tested in production.
Conditions
V_I/O = 0V
V_IN = 0V
8.6 Power-Up Requirements and Reset Behavior
During a power-up sequence, the V_CC supplied to the AT24C01D/02D should monotonically rise from GND to the
minimum V_CC level as specified in Section 8.2 with no greater than a slew rate of 1V/μs.
8.6.1
Device Reset
To prevent Write operations or other spurious events from happening during a power-up sequence, the
AT24C01D/02D includes a Power-On-Reset (POR) circuit. Upon power-up, the device will not respond to any
commands until the V_CC level crosses the internal voltage threshold (V_POR) that brings the device out of reset and
into standby mode.
The system designer must ensure that instructions are not sent to the device until the V_CC supply has reached a
stable value greater than or equal to the minimum V_CC level. Additionally, once the V_CC is greater than or equal to
the minimum V_CC level, the bus Master must wait at least t_PUP before sending the first command to the device. See
Table 8-1 for the values associated with these power-up parameters.
Table 8-1. Power-up Conditions
Symbol Parameter
Min
Max Units
t_PUP
V_POR
t_POFF
Time required after V_CC is stable before the device can accept commands.
Power-On Reset Threshold Voltage
Minimum time at V_CC = 0V between power cycles.
100
μs
1.5
V
1
ms
If an event occurs in the system where the V_CC level supplied to the AT24C01D/02D drops below the maximum
V_POR level specified, it is recommended that a full power cycle sequence be performed by first driving the V_CC pin
to GND, waiting at least the minimum t_POFF time, and then performing a new power-up sequence in compliance
with the requirements defined in this section.
8.7 EEPROM Cell Performance Characteristics
Operation
Write Endurance⁽¹⁾
Test Condition
T_A = 25°C, V_CC(min)< V_CC <V_CC(max)
Byte or Page Write Mode
Min
Max
Units
1,000,000
—
Write Cycles
Data Retention⁽²⁾
T_A = 55°C
100
—
Years
Notes: 1. Write endurance performance is determined through characterization and the qualification process.
2. The data retention capability is determined through qualification and checked on each device in production.
AT24C01D and AT24C02D [DATASHEET] 15
Atmel-8871B-SEEPROM-AT24C01D-02D-Datasheet_032014