AT24C01D_14 Datasheet, PDF (7/26 Pages) ATMEL Corporation – IC-Compatible (2-wire) Serial EEPROM

4. Memory Organization
The AT24C01D is internally organized as 16 pages of 8 bytes each while the AT24C02D is organized as 32 pages
of 8 bytes each.
4.1 Device Addressing
Accessing the device requires an 8-bit Device Address word following a Start condition to enable the device for a
Read or Write operation. Since multiple slave devices can reside on the serial bus, each slave device must have its
own unique address so that the Master can access each device independently.
The most significant four bits of the Device Address word is referred to as the device type identifier. The device
type identifier ‘1010’ (Ah) is required in bits seven through four of the Device Address byte (see Table 4-1.)
Following the 4-bit device type identifier are the hardware slave address bits, A₂, A₁, and A₀. These bits can be
used to expand the address space by allowing up to eight other Serial EEPROM devices on the same bus. The A₂,
A₁, and A₀ values must correlate with the voltage level on the corresponding hardwired input pins, A₂, A₁, and A₀.
These hardwired address pins use an internal proprietary circuit that automatically biases each pin to a Logic 0
state if the pin is allowed to float. In order to operate in a wide variety of application environments, the pull-down
mechanism is intentionally designed to be somewhat strong. Once the pin is biased above the CMOS input buffer’s
trip point (~0.5 x V_CC), the pull-down mechanism disengages. Atmel recommends connecting the A₂, A₁, and A₀
pins to a known state whenever possible.
When using the SOT23 package, the A₂, A₁, and A₀ signals are not accessible and are left floating. The previously
mentioned automatic pull-down circuit will set these signals to a Logic 0 state. As a result, to properly communicate
with the device in the SOT23 package, the A₂, A₁, and A₀ software bits must always be set to Logic 0 for any
operation. This requirement has been shown in Table 4-1.
The eighth bit of the Device Address (bit 0) is the Read/Write operation select bit. A Read operation is initiated if
this bit is high and a Write operation is initiated if this bit is low.
Upon the successful comparison of the Device Address, the EEPROM will return an ACK. If a valid comparison is
not made, the device will NACK and return to a standby state.
Table 4-1. Device Address Byte
Package
SOIC, TSSOP, UDFN,
PDIP, VFBGA
Bit 7
1
Device Type Identifier
Bit 6
Bit 5
0
1
Bit 4
0
Hardware Slave Address Bits
Bit 3
Bit 2
Bit 1
Read/ Write
Bit 0
A₂
A₁
A₀
R/W
SOT23
1
0
1
0
0
0
0
R/W
For all operations except the Current Address Read, a Word Address byte must be transmitted to the device
immediately following the Device Address byte. The Word Address byte contains a 7-bit (in the case of the
AT24C01D) or 8-bit (in the case of the AT24C02D) memory array address, and is used to specify which location in
the EEPROM to start reading or writing. Please refer to Table 4-2 to review these bit positions.
Table 4-2. Word Address Byte
Bit 7
A7⁽¹⁾
Bit 6
A6
Bit 5
A5
Bit 4
A4
Bit 3
A3
Bit 2
A2
Bit 1
A1
Bit 0
A0
Note: 1. The A7 bit is a don’t care bit for the AT24C01D.
The relationship of the AC timing parameters with respect to SCL and SDA for the AT24C01D/02D are shown in
the timing waveform in Figure 8-1 on page 14. The AC timing characteristics and specifications are outlined in
Section 8.4 “AC Characteristics” on page 14.
AT24C01D and AT24C02D [DATASHEET]
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Atmel-8871B-SEEPROM-AT24C01D-02D-Datasheet_032014