AT32UC3L0256_14 Datasheet, PDF (764/852 Pages) ATMEL Corporation – Read-modify-write Instructions and Atomic Bit Manipulation

AT32UC3L0128/256
31.5.3.3
7. Go to Update-DR and re-enter Select-DR Scan.
8. In Shift-DR: For a read operation, scan out the contents of the addressed register. For a
write operation, scan in the new contents of the register.
9. Return to Run-Test/Idle.
For any operation, the full 7 bits of the address must be provided. For write operations, 32 data
bits must be provided, or the result will be undefined. For read operations, shifting may be termi-
nated once the required number of bits have been acquired.
Table 31-19. MEMORY_SERVICE Details
Instructions
Details
IR input value
10100 (0x14)
IR output value
peb01
DR Size
34 bits
DR input value (Address phase)
aaaaaaar xxxxxxxx xxxxxxxx xxxxxxxx xx
DR input value (Data read phase)
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xx
DR input value (Data write phase)
dddddddd dddddddd dddddddd dddddddd xx
DR output value (Address phase)
xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb
DR output value (Data read phase) eb dddddddd dddddddd dddddddd dddddddd
DR output value (Data write phase) xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb
MEMORY_SIZED_ACCESS
This instruction allows access to the entire Service Access Bus data area. Data is accessed
through a 36-bit byte index, a 2-bit size, a direction bit, and 8, 16, or 32 bits of data. Not all units
mapped on the SAB bus may support all sizes of accesses, e.g., some may only support word
accesses.
The data register is alternately interpreted by the SAB as an address register and a data regis-
ter. The SAB starts in address mode after the MEMORY_SIZED_ACCESS instruction is
selected, and toggles between address and data mode each time a data scan completes with
the busy bit cleared.
32145C–06/2013
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