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| AT32UC3L0256_14 Datasheet, PDF (46/852 Pages) ATMEL Corporation – Read-modify-write Instructions and Atomic Bit Manipulation | |||
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AT32UC3L0128/256
The registers can also be manually reset by writing a one to the Channel Reset bit in the PCON-
TROL register (PCONTROL.CH0/1RES). The Performance Channel Read/Write Latency
registers (PRLAT0/1 and PWLAT0/1) are saturating when their maximum count value is
reached. The PRLAT0/1 and PWLAT0/1 registers can only be reset by writing a one to the cor-
responding reset bit in PCONTROL (PCONTROL.CH0/1RES).
A counter is enabled by writing a one to the Channel Enable bit in the Performance Control Reg-
ister (PCONTROL.CH0/1EN).
46
32145Câ06/2013
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