AT32UC3L0256_14 Datasheet, PDF (24/852 Pages) ATMEL Corporation – Read-modify-write Instructions and Atomic Bit Manipulation

AT32UC3L0128/256
Figure 4-5. The Status Register Low Halfword
Bit 15
Bit 0
- T - - - - - - - - L Q V N Z C Bit name
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value
Carry
Zero
Sign
Overflow
Saturation
Lock
Reserved
Scratch
Reserved
4.4.3 Processor States
4.4.3.1
Normal RISC State
The AVR32 processor supports several different execution contexts as shown in Table 4-2.
Table 4-2. Overview of Execution Modes, their Priorities and Privilege Levels.
Priority Mode
Security
Description
1
Non Maskable Interrupt Privileged
Non Maskable high priority interrupt mode
2
Exception
Privileged
Execute exceptions
3
Interrupt 3
Privileged
General purpose interrupt mode
4
Interrupt 2
Privileged
General purpose interrupt mode
5
Interrupt 1
Privileged
General purpose interrupt mode
6
Interrupt 0
Privileged
General purpose interrupt mode
N/A
Supervisor
Privileged
Runs supervisor calls
N/A
Application
Unprivileged Normal program execution mode
4.4.3.2
Mode changes can be made under software control, or can be caused by external interrupts or
exception processing. A mode can be interrupted by a higher priority mode, but never by one
with lower priority. Nested exceptions can be supported with a minimal software overhead.
When running an operating system on the AVR32, user processes will typically execute in the
application mode. The programs executed in this mode are restricted from executing certain
instructions. Furthermore, most system registers together with the upper halfword of the status
register cannot be accessed. Protected memory areas are also not available. All other operating
modes are privileged and are collectively called System Modes. They have full access to all priv-
ileged and unprivileged resources. After a reset, the processor will be in supervisor mode.
Debug State
The AVR32 can be set in a debug state, which allows implementation of software monitor rou-
tines that can read out and alter system information for use during application development. This
implies that all system and application registers, including the status registers and program
counters, are accessible in debug state. The privileged instructions are also available.
All interrupt levels are by default disabled when debug state is entered, but they can individually
be switched on by the monitor routine by clearing the respective mask bit in the status register.
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