AT32UC3L0256_14 Datasheet, PDF (636/852 Pages) ATMEL Corporation – Read-modify-write Instructions and Atomic Bit Manipulation

26.9.16 Channel Disable Register
Name:
CHDR
Access Type:
Write-only
Offset:
0x44
Reset Value:
0x00000000
AT32UC3L0128/256
31
CH31
30
CH30
29
CH29
28
CH28
27
CH27
26
CH26
25
CH25
24
CH24
23
CH23
22
CH22
21
CH21
20
CH20
19
CH19
18
CH18
17
CH17
16
CH16
15
CH15
14
CH14
13
CH13
12
CH12
11
CH11
10
CH10
9
CH9
8
CH8
7
CH7
6
CH6
5
CH5
4
CH4
3
CH3
2
CH2
1
CH1
0
CH0
• CHn: Channel N Disable
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register disables the corresponding channel.
Warning: If the corresponding channel is disabled during a conversion, or if it is disabled and then re-enabled during a
conversion, its associated data and its corresponding DRDY and OVRE bits in SR are unpredictable.
The number of available channels is device dependent. Please refer to the Module Configuration section at the end of this
chapter for information regarding how many channels are implemented.
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