U2739M-B Datasheet, PDF (30/69 Pages) ATMEL Corporation – DAB One-Chip Channel- and Source Decoder

U2739M-B
6.12 HSSO Interface
6.12.1 HSSO Interface Signal Description
QFP144
30
32
34
QFP100
21
22
23
Pin Name
HSSO_WIN
HSSO _CLK
HSSO _DAT
Signal Description
HSSO window signal
HSSO clock signal
HSSO data signal
Pad Type Dir. 5 V Tol.
PRO04T
out
PRO04T
out
PRO04T
out
6.12.2 HSSO Interface Description
The High Speed Serial Output (HSSO) is a standard 3-line
output interface implemented to give out data bursts in a
multiplexed way. Up to 4 applications can be given out
simultaneously:
D Channel Impulse Response (CIR)
D Data decoder 1
D Data decoder 2
D Programme Associated Data (PAD)
The HSSO can be configured using the ’set HSSO / RS232
configuration’ MC command (see section 8). Each HSSO
burst consists of a header word followed by n data words
(as indicated in the header).
HSSO-ID
(Burst Identifier)
Length
(Number of Transmitted Data Words n Without Header Word)
bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CIR
0000
Number of CIR words
DD1
0001
Number of DD1 words
DD2
0010
Number of DD2 words
PAD
0011
Number of PAD words
6.12.3 HSSO Interface Timing Diagram
tclk
tH tL
HSSO_CLK
HSSO_WIN
HSSO_DAT
td1
15 14 13
td2
header
1
0
15 14 13
1
0
15
0
15
14
1
0
Data 0
Data n–1
Figure 19. HSSO interface timing diagram
6.12.4 HSSO Interface Timing Parameters
Parameter
HSSO clock period
HSSO clock high
HSSO clock low
HSSO_WIN output delay
HSSO_DAT output delay
Symbol Min.
Typ.
Max.
Unit
tclk
4.07
us
tH
2.035
us
tL
2.035
us
td1
–5.0
0.0
5.0
ns
td2
–5.0
0.0
5.0
ns
30 (69)
Rev. A1, 22-May-01