U2739M-B Datasheet, PDF (25/69 Pages) ATMEL Corporation – DAB One-Chip Channel- and Source Decoder

U2739M-B
6.8.6 SP-DIF Interface Description
The SP-DIF format is frame based, which means one
frame represents one audio sampling period. Every frame
comprises 2 subframes a 32 bit referring to the left and
right sample. The data is transmitted in bi-phase coded
format. The frame synchronization pattern are based on
biphase violations and indicate whether a left or right
subframe follows.
The last 4 bi-phase coded bits of each subframe represent
the V (validity flag), U (user channel data), C (channel
status data) and P (parity) information as described in the
SP-DIF specification.
Complete frames (left and right sample according to
64 2 bit due to bi-phase coding) are transmitted at the
audio sampling rate (48 resp. 24 kHz).
6.8.7 SP-DIF Interface Timing
Parameter
The SP-DIF interface was designed according the digital
audio interface IEC958 specification [CEI/ISO 958
Digital Audio Interface Standard].
6.8.8 SP-DIF Interface Timing Diagram
SPDIF
S3 S2 S1
Frame sync. pattern
8 Zero’s (bi–phase coded)
A0
A1
A2
A14
A15
Audio data bits (bi–phase coded)
V
U
C
P
Flag bits (bi–phase coded)
SP–DIF subframe (left or right audio sample)
Figure 14. SP-DIF interface timing diagram
6.9 RDI Interface
6.9.1 RDI Interface Signal Description
QFP144 QFP100
Pin Name
64
46 C_DATA5/RDI_VBIT
85
60 RDI_RX
86
61 RDI_TX
Signal Description
C–bus data bit 5 (pull down)
RDI receive data
RDI transmit data
Pad Type
PRD04TZ
PDIZ
PRO04T
Dir.
inout
in
out
5 V Tol.
x
x
6.9.2 RDI Interface Description
The RDI interface is designed according to the ‘Digital
Audio Broadcasting System: Specification of the
Receiver Data Interface (RDI)’ [Digital Audio
Broadcasting System: Specification of the Receiver Data
Interface (RDI), Issue 1.4]. The RDI frames are
embedded into the IEC 958 interface. The RDI output
data is provided in the extended format of the high
capacity mode. Further the RDI Control Channel (RCC)
can be implemented according to the preliminary specifi-
cation [Digital Audio Broadcasting System: Preliminary
Specification of the RDI Control Channel], [Proposal of
DAB Command Set for Receiver (DCSR)].
6.9.3 RDI Interface Timing Diagram
RDI_TX/RX
tH
tL
2 * tH
2 * tL
3 * tH
3 * tL
Figure 15. RDI interface timing diagram
Rev. A1, 22-May-01
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