U2739M-B Datasheet, PDF (24/69 Pages) ATMEL Corporation – DAB One-Chip Channel- and Source Decoder

U2739M-B
6.8 Audio Interfaces
6.8.1 I2S Interface Signal Description
QFP144 QFP100 Pin Name
79
56 I2S_CLK
80
57 I2S_DAT
82
58 I2S_WIN
Signal Description
I2S clock line
I2S data line
I2S window line
Pad Type
PRO04T
PRO04T
PRO04T
Dir. 5 V Tol.
out
out
out
6.8.2 I2S Interface Description
The I2S interface is a standard continuous audio interface
consisting of bit clock (_CLK), word select (_WIN) and
data (_DAT) lines. The word select line indicates the
transmitted channel: LOW for left, HIGH for right. Please
be aware of the 1 cycle delay of the data word MSB
corresponding to the I2S_WIN edge !
As in the DAB system the I2S_WIN clock is fixed as
48 kHz (MPEG1) or 24 kHz (MPEG2) the bit clock
depends on the data word length. The standard word
length is 16 bit, hence the bit clock is fixed at 1.536 MHz
resp. 768 kHz.
6.8.3
I2S_CLK
I2S Interface Timing Diagram
tclk
tH tL
I2S_WIN
I2S_DAT
td1
0
15
14
13
12
td2
3
2
1
0
15
14
13
12
3
2
1
0
15 14 13 12
left sample
right sample
Figure 13. I2S interface timing diagram
6.8.4 I2S Interface Timing Parameter
Parameter
I2S clock period
I2S clock high
I2S clock low
I2S_WIN output delay
I2S_DAT output delay
Symbol
tclk
tH
tL
td1
td2
Min.
–5.0
–5.0
6.8.5 SP-DIF Interface Signal Description
QFP144 QFP100
Pin Name
77
54 SPDIF
Signal Description
SPDIF output
Typ.
Max.
Unit
16.28
us
14.28
us
14.28
us
0.0
5.0
ns
0.0
5.0
ns
Pad Type Dir. 5 V Tol.
PRO04T
out
24 (69)
Rev. A1, 22-May-01