U2739M-B Datasheet, PDF (15/69 Pages) ATMEL Corporation – DAB One-Chip Channel- and Source Decoder

U2739M-B
6.2.2 ADC Interface Description
The ADC interface as shown in figure 6 consists of the
ADC data input signal ADC_DATA(9:0) and the ADC
sampling clock output signal ADC_CLK. The
U2739M-B can be connected to every standard AD with
either binary or 2’s complement output format. The
sampling frequency is 8.192 MHz and a bandwidth of
2 MHz is necessary. The possible IF’s, which are
supported in conjunction with the IF input signal mode
(parameter IFM) are given by the formula.
f_if = 2.048 MHz + n 4.096 MHz, with n = 0, 1, 2, 3 ....
Thus possible IFs are 2.048 MHz, 6.144 MHz, ...
38.912 MHz. The parameter IFM is defined by the
MC command ‘set global configuration’ [Atmel Wireless
& Microcontrollers U2739M documentation set –
“U2739M_MC_Command_set_vxxx.pdf”]. The analog
input bandwidth of the A/D converter must be chosen
accordingly. The ADC_DATA input is 10 bit wide. The
typical output delay (td3 in figure 7) of the AD converter
related to the falling edge of the sampling clock CLK8192
should be 20 ns. The generated 8.192 MHz output clock
take over the ADC_DATA with his rising edge of
ADC_CLK. The format ‘binary offset’ or ‘2’s
complement’ of the A/D converter can be selected by the
parameter ADCF. This parameter is also defined by the
‘set global configuration’ MC command [Atmel Wireless
& Microcontrollers U2739M documentation set –
“U2739M_MC_Command_set_vxxx.pdf”].
Furthermore, the sampling clock generation is performed
by the U2739M-B. The input data appearing at the
ADC_DATA port are assumed to be generated by an A/D
converter. The effective resolution of this converter
should be greater than 9 bit in order to use the full
dynamic range implemented in the U2739M-B. The
sampling clock required for the external A/D converter is
derived inside U2739M-B. It has to be 8.192 MHz.
6.2.3 ADC Interface Timing Diagram
XIN
ADC_CLK
td1
td1
tc8 H
tc8
tc8 L
tclk
tH tL
ADC_D[9:0]
ts1
Figure 7. ADC interface timing diagram
6.2.4 ADC Interface Timing Parameters
Parameter
XIN clock period
XIN clock high
XIN clock low
ADC_CLK clock period
ADC_CLK clock high
ADC_CLK clock low
Setup time ADC_D(9:0)
Output delay of ADC_CLK
Symbol Min.
Typ.
Max.
Unit
tclk
40.7
ns
tH
15.0
20.35
25.0
ns
tL
15.0
20.35
25.0
ns
tc8
3 × 40.7
ns
tc8H
1 × 40.7
ns
tc8L
2 × 40.7
ns
ts1
5.0
ns
td1
12.0
20.0
28.0
ns
Rev. A1, 22-May-01
15 (69)