U2739M-B Datasheet, PDF (14/69 Pages) ATMEL Corporation – DAB One-Chip Channel- and Source Decoder

U2739M-B
6 Interface Description
6.1 Overview
The interface description explains the purpose, the
utilization and the meaning of every interface and every
signal. It is divided into twelve sections, which are related
to the different interfaces. An overview of all interfaces
is shown in the functional block diagram below. Several
standard output interfaces like I²S or SPDIF are used to
offer a flexible usage of the U2739M-B.
SRAM
ADC
TUNER
PWM
IQ splitting
filtering
AFC
AGC
De-
modulation
FSYNC
generation
W_AGC
FSYNC
FS_IN
SLI
Time
synchro–
nization
AMD
dF
Frequency
synchro–
nization
De-
interleaving
Decodeing
TII decoding
(USE)
Status
generation
Channel
decoder
VCXO
tank
XO
UNIT
Audio
source
decoding
PAD
extraction
Source decoder
Data
decoder 1
(FIDC)
Data
decoder 2
(AIC (USE))
Data decoder
I2S
DAC
SPDIF
V24/RS232
ROM
BOOT
UNIT
U2739M-B
HSSO
MC
interface
MC
memory
MC interface
MC
RDI
controller
RDI interface
SFCO
RDI_TX
RDI_RX
Figure 6. Functional block diagram
6.2 ADC Interface
6.2.1 ADC Interface Signal Description
QFP144
1
4
5
6
7
10
11
12
13
16
17
QFP100
1
2
3
4
5
6
7
8
9
10
11
Pin Name
ADC_CLK
ADC_DATA9
ADC_DATA8
ADC_DATA7
ADC_DATA6
ADC_DATA5
ADC_DATA4
ADC_DATA3
ADC_DATA2
ADC_DATA1
ADC_DATA0
Signal Description
ADC sampling clock output 8.192 MHz
ADC data input, bit 9 (MSB)
ADC data input, bit 8
ADC data input, bit 7
ADC data input, bit 6
ADC data input, bit 5
ADC data input, bit 4
ADC data input, bit 3
ADC data input, bit 2
ADC data input, bit 1
ADC data input, bit 0 (LSB)
Pad Type
PDO04T
PDIZ
PDIZ
PDIZ
PDIZ
PDIZ
PDIZ
PDIZ
PDIZ
PDIZ
PDIZ
Dir. 5 V Tol.
out
in
x
in
x
in
x
in
x
in
x
in
x
in
x
in
x
in
x
in
x
14 (69)
Rev. A1, 22-May-01