AMC0XXDFLKA Datasheet, PDF (15/46 Pages) Advanced Micro Devices – 4, 8, 20, or 32 Megabyte 5.0 Volt-only Flash Memory PC Card

Start
Write Embedded Write Command
Sequence per Table 3 or 4
Data Poll Device
Increment Address
No
Verify Byte
Yes
No
Last
Address
Yes
Completed
Figure 2. Embedded Programming Algorithm in Byte-Wide Mode
19521D-3
The Reset command will safely reset the segment
memory to the Read mode. Memory contents are not
altered. Following any other command, write the Reset
command once to the segment. This will safely abort
any operation and reset the device to the Read mode.
The Reset is needed to terminate the auto select oper-
ation. It can be used to terminate an Erase or Sector
Erase operation, but the data in the sector or segment
being erased would then be undefined.
Write Operation Status
RY/BY
Ready/Busy
The D-Series Card provides a RY/BY output pin as a
way to indicate to the host system that the Embedded
Algorithms are either in progress or has been com-
pleted. If the output is low, the card is busy with either
a program or erase operation. If the output is high, the
card is ready to accept any read/write or erase opera-
tion. When the RY/BY pin is low, the card will not accept
any additional program or erase commands with the
exception of the Erase Suspend command to the same
device pair, one can still write or erase to a different de-
vice pair. If the card is placed in an Erase Suspend
mode, the RY/BY output will be high.
During programming, the RY/BY pin is driven low after
the rising edge of the fourth WE pulse. During an erase
operation, the RY/BY pin is driven low after the rising
edge of the sixth WE pulse. The RY/BY pin will indicate
a busy condition during the RESET pulse. Refer to Fig-
ure 21 for a detailed timing diagram. The RY/BY pin is
pulled high in standby mode. RY/BY is best used to in-
terrupt the CPU when an erase completes. Polling is
best for byte programming.
Data Polling—D7 (D15 on Odd Byte)
The Flash Memory PC Card features Data Polling as a
method to indicate to the host system that the Embed-
ded algorithms are either in progress or completed.
While the Embedded Programming algorithm is in op-
eration, an attempt to read the device will produce the
complement of expected valid data on D7 of the ad-
dressed memory sector or memory segment. Upon
completion of the Embedded Program algorithm an at-
tempt to read the device will produce valid data on D7.
The Data Polling feature is valid after the rising edge of
the fourth WE pulse of the four write pulse sequence.
While the Embedded Erase algorithm is in operation,
D7 will read “0” until the erase operation is completed.
Upon completion of the erase operation, the data on D7
will read “1”.
The Data Polling feature is only active during the Em-
bedded Programming or Erase algorithms. Please note
that the AmC0XXDFLKA data pin (D7) may change
asynchronously while Output Enable (OE) is asserted
low. This means that the device is driving status infor-
mation on D7 at one instant of time and then the byte’s
valid data at the next instant of time. Depending on
AmC0XXDFLKA
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