AMC0XXDFLKA Datasheet, PDF (13/46 Pages) Advanced Micro Devices – 4, 8, 20, or 32 Megabyte 5.0 Volt-only Flash Memory PC Card

FLASH MEMORY PROGRAM/ERASE
OPERATIONS
Details of AMD’s Embedded Write and
Erase Operations
Embedded Erase Algorithm
The automatic memory sector or memory segment
erase does not require the device to be entirely
pre-programmed prior to executing the Embedded
Erase command. Upon executing the Embedded Erase
command sequence, the addressed memory sector or
memory segment will automatically write and verify the
entire memory segment or memory sector for an all
“zero” data pattern. The system is not required to pro-
vide any controls or timing during these operations.
When the memory sector or memory segment is au-
tomatically verified to contain an all “zero” pattern, a
self-timed chip erase-and-verify begins. The erase
and verify operations are complete when the data on
D7 (D15 on the odd byte) of the memory sector or
memory segment is “1” (see Write Operation Status
section) at which time the device returns to the Read
mode. The system is not required to provide any con-
trol or timing during these operations. A Reset com-
mand after the device has begun execution will stop
the device but the data in the operated segment will
be undefined. In that case, restart the erase on that
sector and allow it to complete.
When using the Embedded Erase algorithm, the erase
automatically terminates when adequate erase margin
has been achieved for the memory array (no erase ver-
ify command is required). The margin voltages are in-
ternally generated in the same manner as when the
standard erase verify command is used.
The Embedded Erase command sequence is a com-
mand only operation that stages the memory sector or
memory segment for automatic electrical erasure of all
bytes in the array. The automatic erase begins on the
rising edge of the WE and terminates when the data on
D7 of the memory sector or memory segment is “1”
(see Write Operation Status section) at which time the
device returns to the Read mode. Please note that for
the memory segment or memory sector erase opera-
tion, Data Polling may be performed at any address in
that segment or sector.
Figure 1 and Table 6 illustrate the Embedded Erase Al-
gorithm, a typical command string and bus operations.
As described earlier, once the memory sector in a de-
vice or memory segment completes the Embedded
Erase operation it returns to the Read mode and ad-
dresses are no longer latched. Therefore, the device
requires that the address of the sector being erased is
supplied by the system at this particular instant of time.
Otherwise, the system will never read a “1” on D7. A
Table 6. Embedded Erase Algorithm
Bus Operation
Command
Comments
Standby
Write
Wait for V_CC ramp
Embedded Erase
command sequence
6 bus cycle
operation
Read
Data Polling to
verify erasure
system designer has two choices to implement the Em-
bedded Erase algorithm:
1. The system (CPU) keeps the sector address (within
any of the sectors being erased) valid during the en-
tire Embedded Erase operation, or
2. Once the system executes the Embedded Erase
command sequence, the CPU takes away the ad-
dress from the device and becomes free to do other
tasks. In this case, the CPU is required to keep track
of the valid sector address by loading it into a tem-
porary register. When the CPU comes back for per-
forming Data Polling, it should reassert the same
address.
Since the Embedded Erase operation takes a signifi-
cant amount of time (1 s–30 s), option 2 makes more
sense. However, the choice of these two options has
been left to the system designer.
Figure 1 and Table 6 illustrate the Embedded Erase Al-
gorithm, a typical command string and bus operations.
Sector Erase
Sector erase is a six bus cycle operation. There are
two “unlock” write cycles. These are followed by writ-
ing the “set up” command. Two more “unlock” write cy-
cles are then followed by the sector erase command.
The sector address (any address location within the
desired sector) is latched on the falling edge of WE,
while the command (data) is latched on the rising
edge of WE. A time-out of 50 µs from the rising edge
of the last sector erase command will initiate the sec-
tor erase command(s).
Multiple sectors may be erased by writing the six bus
cycle operations as described above. This sequence is
followed with writes of the sector erase command 30H
to addresses in other sectors to be erased. A time-out
of 50 µs from the rising edge of the WE pulse for the
last sector erase command will initiate the sector erase.
If another sector erase command is written within the
50 µs time-out window the timer is reset. Any command
other than sector erase within the time-out window will
reset the device to the read mode, ignoring the previ-
ous command string (refer to Write Operation Status
section for Sector Erase Timer operation). Loading the
sector erase buffer may be done in any sequence and
with anysector number.
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