EP4SGX360KF40C4N Datasheet, PDF (74/82 Pages) Altera Corporation – Device Datasheet and Addendum for Stratix IV Devices

1–66
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Glossary
Table 1–54. Glossary Table (Part 3 of 4)
Letter
Subject
SW (sampling
window)
Definitions
Timing Diagram—the period of time during which the data must be valid in order to capture
it correctly. The setup and hold times determine the ideal strobe position within the sampling
window, as shown:
Bit Time
0.5 x TCCS
RSKM
Sampling Window
(SW)
RSKM
0.5 x TCCS
The JEDEC standard for SSTl and HSTL I/O defines both the AC and DC input signal values.
The AC values indicate the voltage levels at which the receiver must meet its timing
specifications. The DC values indicate the voltage levels at which the final logic state of the
receiver is unambiguously defined. After the receiver input has crossed the AC value, the
receiver changes to the new logic state.
The new logic state is then maintained as long as the input stays beyond the AC threshold.
This approach is intended to provide predictable receiver timing in the presence of input
S
waveform ringing, as shown:
Single-ended
voltage
referenced I/O
standard
Single-Ended Voltage Referenced I/O Standard
VOH
V_REF
V_CCIO
VIH (AC )
VIH(DC)
VIL (D C)
VIL (AC )
VOL
V_SS
t_C
TCCS (channel-
to-channel-skew)
High-speed receiver/transmitter input and output clock period.
The timing difference between the fastest and slowest output edges, including t_CO variation
and clock skew, across channels driven by the same PLL. The clock is included in the TCCS
measurement (refer to the Timing Diagram figure under SW in this table).
High-speed I/O block: Duty cycle on high-speed transmitter output clock.
t_DUTY
T
t_FALL
t_INCCJ
t_{OUTPJ_IO}
t_{OUTPJ_DC}
t_RISE
U
—
Timing Unit Interval (TUI)
The timing budget allowed for skew, propagation delays, and data sampling window.
(TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = t_C/w)
Signal high-to-low transition time (80-20%)
Cycle-to-cycle jitter tolerance on the PLL clock input
Period jitter on the general purpose I/O driven by a PLL
Period jitter on the dedicated clock output driven by a PLL
Signal low-to-high transition time (20-80%)
—
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
January 2014 Altera Corporation