EP4SGX360KF40C4N Datasheet, PDF (70/82 Pages) Altera Corporation – Device Datasheet and Addendum for Stratix IV Devices

1–62
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
I/O Timing
Figure 1–7 shows the timing diagram for the oe and dyn_term_ctrl signals.
Figure 1–7. Timing Diagram for the oe and dyn_term_ctrl Signals
Tristate
R_X
T_X
Tristate
R_X
oe
dyn_term_ctrl
T_{RS_RT}
T_{RS_RT}
Duty Cycle Distortion (DCD) Specifications
Table 1–51 lists the worst-case DCD for Stratix IV devices.
Table 1–51. Worst-Case DCD on Stratix IV I/O Pins ⁽¹⁾
Symbol
–2/–2×
–3
–4
Speed Grade
Speed Grade Speed Grade
Unit
Min
Max Min Max Min Max
Output Duty Cycle
45
55
45
55
45
55
%
Note to Table 1–51:
(1) The listed specification is only applicable to the output buffer across different I/O standards.
I/O Timing
Altera offers two ways to determine I/O timing—the Excel-based I/O Timing and the
Quartus II Timing Analyzer.
Excel-based I/O Timing provides pin timing performance for each device density and
speed grade. The data is typically used prior to designing the FPGA to get an estimate
of the timing budget as part of the link timing analysis. The Quartus II Timing
Analyzer provides a more accurate and precise I/O timing data based on the specifics
of the design after you complete place-and-route.
f The Excel-based I/O Timing spreadsheet is downloadable from the Literature:
Stratix IV Devices webpage.
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
January 2014 Altera Corporation