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EP4SGX360KF40C4N Datasheet, PDF (56/82 Pages) Altera Corporation – Device Datasheet and Addendum for Stratix IV Devices | |||
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1â48
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
PLL Specifications
Table 1â34 lists the Stratix IV PLL specifications when operating in the commercial
(0° to 85°C), industrial (â40° to 100°C), and military (â55°C to 125°C) junction
temperature ranges.
Table 1â34. PLL Specifications for Stratix IV Devices (Part 1 of 2)
Symbol
Parameter
Min Typ
Input clock frequency (â2/â2x speed grade)
5
â
fIN
Input clock frequency (â3 speed grade)
Input clock frequency (â4 speed grade)
5
â
5
â
fINPFD
Input frequency to the PFD
PLL VCO operating range (â2 speed grade)
5
â
600 â
fVCO (2)
PLL VCO operating range (â3 speed grade)
PLL VCO operating range (â4 speed grade)
600 â
600 â
tEINDUTY
Input clock or external feedback clock input duty cycle
Output frequency for internal global or regional clock
(â2/â2x speed grade)
40
â
â
â
fOUT
Output frequency for internal global or regional clock
(â3 speed grade)
â
â
Output frequency for internal global or regional clock
(â4 speed grade)
â
â
Output frequency for external clock output (â2 speed grade) â
â
fOUT_EXT
Output frequency for external clock output (â3 speed grade) â
â
Output frequency for external clock output (â4 speed grade) â
â
tOUTDUTY
tFCOMP
Duty cycle for external clock output (when set to 50%)
External feedback clock compensation time
45
50
â
â
tCONFIGPLL
Time required to reconfigure scan chain
â 3.5
tCONFIGPHASE Time required to reconfigure phase shift
â
1
fSCANCLK
tLOCK
scanclk frequency
â
â
Time required to lock from end-of-device configuration or
de-assertion of areset
â
â
tDLOCK
Time required to lock dynamically (after switchover or
reconfiguring any non-post-scale counters/delays)
â
â
PLL closed-loop low bandwidth
â 0.3
fCLBW
PLL closed-loop medium bandwidth
PLL closed-loop high bandwidth (8)
â 1.5
â
4
tPLL_PSERR
Accuracy of PLL phase shift
â
â
tARESET
Minimum pulse width on the areset signal
10
â
tINCCJ (4), (5)
Input clock cycle to cycle jitter (FREF ⥠100 MHz)
Input clock cycle to cycle jitter (FREF < 100 MHz)
â
â
â
â
tOUTPJ_DC (6)
Period Jitter for dedicated clock output (FOUT ⥠100 MHz)
Period Jitter for dedicated clock output (FOUT < 100 MHz)
â
â
â
â
Max
800 (1)
717 (1)
717 (1)
325
1600
1300
1300
60
800 (3)
717 (3)
717 (3)
800 (3)
717 (3)
717 (3)
55
10
â
â
100
1
1
â
â
â
±50
â
0.15
±750
175
17.5
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
%
MHz
MHz
MHz
MHz
MHz
MHz
%
ns
scanclk
cycles
scanclk
cycles
MHz
ms
ms
MHz
MHz
MHz
ps
ns
UI (p-p)
ps (p-p)
ps (p-p)
mUI (p-p)
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
January 2014 Altera Corporation
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