EP4SGX360KF40C4N Datasheet, PDF (71/82 Pages) Altera Corporation – Device Datasheet and Addendum for Stratix IV Devices

Chapter 1: DC and Switching Characteristics for Stratix IV Devices
I/O Timing
1–63
Programmable IOE Delay
Table 1–52 lists the Stratix IV IOE programmable delay settings.
Table 1–52. IOE Programmable Delay for Stratix IV Devices
Fast Model
Slow Model
Parameter Available Min Offset
(1)
Settings
(2)
Industrial/
Military
Commercial
(3)
C2 ⁽³⁾
C3
C4 I3/M3 I4
Unit
D1
16
0
0.462
0.505
0.732 0.795 0.857 0.801 0.864 ns
D2
8
0
0.234
0.232
0.337 0.372 0.407 0.371 0.405 ns
D3
8
0
1.700
1.769
2.695 2.927 3.157 2.948 3.178 ns
D4
16
0
0.508
0.554
0.813 0.882 0.952 0.889 0.959 ns
D5
16
0
0.472
0.500
0.747 0.799 0.875 0.817 0.882 ns
D6
8
0
0.186
0.195
0.294 0.319 0.345 0.321 0.347 ns
Notes to Table 1–52:
(1) You can set this value in the Quartus II software by selecting D1, D2, D3, D4, D5, and D6 in the Assignment Name column.
(2) Minimum offset does not include the intrinsic delay.
(3) For the EP4SGX530 device density, the IOE programmable delays have an additional 5% maximum offset.
Programmable Output Buffer Delay
Table 1–53 lists the delay chain settings that control the rising and falling edge delays
of the output buffer. The default delay is 0 ps.
Table 1–53. Programmable Output Buffer Delay ⁽¹⁾
Symbol
Parameter
Typical
Unit
0 (default)
ps
D_OUTBUF
Rising and/or falling edge
50
ps
delay
100
ps
150
ps
Note to Table 1–53:
(1) You can set the programmable output buffer delay in the Quartus II software by setting the Output Buffer Delay
Control assignment to either positive, negative, or both edges, with the specific values stated here (in ps) for the
Output Buffer Delay assignment.
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum