EP4SGX360KF40C4N Datasheet, PDF (54/82 Pages) Altera Corporation – Device Datasheet and Addendum for Stratix IV Devices

1–46
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
Table 1–31. Transceiver Jitter Specifications for Protocols by Stratix IV GT Devices (Part 2 of 2)
Symbol/
Description
Conditions
–1 Industrial Speed –2 Industrial Speed –3 Industrial Speed
Grade
Grade
Grade
Unit
Min Typ Max Min Typ Max Min Typ Max
Jitter Frequency = 40 KHz
Pattern = PRBS-31
>5
>5
—
UI
Equalization = Disabled
Sinusoidal Jitter ^{BER = 1E-12}
tolerance
Jitter Frequency  4 MHz
Pattern = PRBS-31
Equalization = Disabled
> 0.05
> 0.05
—
UI
BER = 1E-12
Notes to Table 1–31:
(1) The jitter numbers for XLAUI/CAUI are compliant to the IEEE P802.3ba specification.
(2) Stratix IV GT transceivers are compliant to the XFI datacom transmitter jitter specifications in Table 9 of XFP Revision 4.1.
(3) Contact Altera for board and link best practices at BER = 1E-15.
Table 1–32 lists the SFI-S transmitter jitter specifications for Stratix IV GT devices.
Table 1–32. SFI-S Transmitter Jitter Specifications for Stratix IV GT Devices ⁽¹⁾, ⁽²⁾
Symbol/Description
Conditions
-1 Industrial -2 Industrial -3 Industrial
Speed Grade Speed Grade Speed Grade _Unit
Mean
Mean
Mean
Pattern = PRBS-31
Total Transmitter jitter at ^{Vod = 800 mV}
11.3 Gbps ⁽⁴⁾
REFCLK = 706.25 MHz
0.23 UI ⁽³⁾
—
—
UI
12 channels in Basic ×1 mode
Notes to Table 1–32:
(1) Dedicated refclk pins were used to drive the input reference clocks.
(2) The jitter numbers are valid for stated conditions only.
(3) Two hundred channels were characterized to derive the mean transmitter jitter specification of 0.23 UI. The maximum jitter across the 200 units
characterized was 0.30 UI.
(4) Contact Altera for board and link best practices at BER = 1E-15.
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
January 2014 Altera Corporation