EP4SGX360KF40C4N Datasheet, PDF (34/82 Pages) Altera Corporation – Device Datasheet and Addendum for Stratix IV Devices

Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
1–26
Table 1–24. Transceiver Specifications for Stratix IV GT Devices (Part 2 of 8)
Symbol/
Description
Conditions
Rise/fall time
Duty cycle
Peak-to-peak
differential input
voltage
On-chip termination
resistors
V_ICM
Transmitter REFCLK
Phase Noise
Transmitter REFCLK
Phase Jitter (rms)
for 100 MHz
REFCLK ⁽²⁾
R_REF
—
—
—
—
—
10 Hz
100 Hz
1 KHz
10 KHz
100 KHz
 1 MHz
10 KHz to
20 MHz
—
–1 Industrial Speed
Grade
Min Typ Max
— — 0.2
45 — 55
–2 Industrial Speed
Grade
Min Typ Max
— — 0.2
45 — 55
–3 Industrial Speed
Grade
Min Typ Max
— — 0.2
45 —
55
200 — 1200 200 — 1200 200 — 1200
— 100 —
1200 ± 10%
— — -50
— — -80
— — -110
— — -120
— — -120
— — -130
— 100 —
1200 ± 10%
— — -50
— — -80
— — -110
— — -120
— — -120
— — -130
— 100 —
1200 ± 10%
— — -50
— — -80
— — -110
— — -120
— — -120
— — -130
— — 3 ——
3
——
3
—
—
2000
± 1%
—
2000
± 1%
—
—
2000
± 1%
—
Transceiver Clocks
Calibration block
clock frequency
—
10 — 125 10 — 125 10 — 125
Dynamic
2.5/
2.5/
2.5/
reconfig_clk
clock frequency
reconfiguration 37.5 —
clock frequency ⁽¹⁾
— 37.5 —
(1)
50 37.5 —
(1)
50
fixedclk clock
frequency
PCIe Receiver
Detect
— 125 —
— 125
—
— 125 —
Delta time between
reconfig_clks
—
(15)
— — 2 ——
2
——
2
Transceiver block
minimum
(gxb_powerdown)
—
power-down pulse
width
— 1 — —1
—
—1
—
Receiver
Supported I/O
Standards
Data rate (Single
width,
—
non-PMA Direct) ⁽¹⁶⁾
1.4 V PCML, 1.5 V PCML, 2.5 V PCML, LVPECL, LVDS
600 — 3750 600 — 3750 600 — 3750
Unit
UI
%
mV

mV
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ps

MHz
MHz
MHz
ms
µs
Mbps
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum