EP4SGX360KF40C4N Datasheet, PDF (73/82 Pages) Altera Corporation – Device Datasheet and Addendum for Stratix IV Devices

Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Glossary
Table 1–54. Glossary Table (Part 2 of 4)
Letter
Subject
Definitions
J
High-speed I/O block: Deserialization factor (width of parallel data bus).
JTAG Timing Specifications:
TMS
TDI
J _{JTAG Timing}
Specifications
TCK
TDO
t _JCP
t _JCH
t _JCL
t_JPZX
t _JPSU
t_JPCO
t _JPH
t _JPXZ
K, L,
M, N, O
—
P
PLL
Specifications
Q
—
R R_L
—
Diagram of PLL Specifications ⁽¹⁾
CLK
Core Clock
Switchover
fIN
fINPFD
N
PFD
CP
LF
VCO fVCO
CLKOUT Pins
fOUT_EXT
Counters
C0..C9
fOUT
GCLK
Key
Reconfigurable in User Mode
M
External Feedback
RCLK
Note:
(1) Core Clock can only be fed by dedicated clock input pins or PLL outputs.
—
Receiver differential input discrete resistor (external to Stratix IV device).
1–65
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum