EP4SGX360KF40C3N Datasheet, PDF (62/82 Pages) Altera Corporation – This chapter covers the electrical and switching characteristics for Stratix IV devices

1–54
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
Chip-Wide Reset (Dev_CLRn) Specifications
Table 1–41 lists the specifications for the Stratix IV chip-wide reset (Dev_CLRn). This
specifications denote the minimum pulse width of the Dev_CLRn signal required to
clear all the device registers.
Table 1–41. Chip-Wide Reset (DEV_CLRn) Specifications
Description
Min
Typ
Dev_CLRn
500
—
Max
Unit
—
s
Periphery Performance
This section describes periphery performance, including high-speed I/O and external
memory interface.
I/O performance supports several system interfaces, such as the LVDS high-speed
I/O interface, external memory interface, and the PCI/PCI-X bus interface.
General-purpose I/O standards such as 3.3-, 2.5-, 1.8-, and 1.5-LVTTL/LVCMOS are
capable of typical 167 MHz and 1.2 LVCMOS at 100 MHz interfacing frequency with
10 pF load.
For the Stratix IV GT –1 and –2 speed grade specifications, refer to the –2/–2× speed
grade column. For the Stratix IV GT –3 speed grade specification, refer to the –3 speed
grade column, unless otherwise specified.
1 Actual achievable frequency depends on design- and system-specific factors. You
must perform HSPICE/IBIS simulations based on your specific design and system
setup to determine the maximum achievable frequency in your system.
High-Speed I/O Specification
Table 1–42 lists the high-speed I/O timing for Stratix IV devices.
Table 1–42. High-Speed I/O Specifications ⁽¹⁾, ⁽²⁾ (Part 1 of 3)
Symbol
Conditions
–2/–2× Speed Grade –3 Speed Grade
–4 Speed Grade
Unit
Min Typ Max Min Typ Max Min Typ Max
f_{HSCLK_in} (input
clock frequency) Clock boost factor W = 1 to 40
True Differential I/O
(3)
5
— 800
5
— 717
5
— 717 MHz
Standards
f_{HSCLK_in} (input
clock frequency)
Single Ended I/O
Clock boost factor W = 1 to 40
(3)
5
— 800
5
— 717
5
— 717 MHz
Standards ⁽¹⁰⁾
f_{HSCLK_in} (input
clock frequency)
Single Ended I/O
Clock boost factor W = 1 to 40
(3)
5
— 520
5
— 420
5
— 420 MHz
Standards ⁽¹¹⁾
f_{HSCLK_OUT} (output
clock frequency)
—
5
—
800
(8)
5
—
717
(8)
5
—
717
(8)
MHz
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
July 2012 Altera Corporation