EP4SGX360KF40C3N Datasheet, PDF (14/82 Pages) Altera Corporation – This chapter covers the electrical and switching characteristics for Stratix IV devices

Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–6
Electrical Characteristics
Table 1–6. Recommended Operating Conditions for Stratix IV Devices (Part 2 of 2)
Symbol
Description
Condition Minimum Typical
t_RAMP
Power supply ramp time
Normal POR
(PORSEL=0)
0.05
—
Fast POR
(PORSEL=1)
0.05
—
Notes to Table 1–6:
(1) If you do not use the volatile security key, you may connect the V_CCBAT to either GND or a 3.0-V power supply.
(2) V_CCPD must be 2.5 V when V_CCIO is 2.5, 1.8, 1.5, or 1.2 V. V_CCPD must be 3.0 V when V_CCIO is 3.0 V.
Maximum Unit
100
ms
4
ms
Table 1–7 lists the transceiver power supply recommended operating conditions for
Stratix IV GX devices.
Table 1–7. Transceiver Power Supply Operating Conditions for Stratix IV GX Devices ⁽¹⁾
Symbol
Description
Minimum Typical Maximum Unit
V_{CCA_L}
V_{CCA_R}
Transceiver high voltage power (left side)
Transceiver high voltage power (right side)
2.85/2.375 3.0/2.5 ⁽²⁾ 3.15/2.625 V
V_{CCHIP_L}
Transceiver HIP digital power (left side)
0.87
0.9
0.93
V
V_{CCHIP_R}
Transceiver HIP digital power (right side)
0.87
0.9
0.93
V
V_{CCR_L}
Receiver power (left side)
1.045
1.1
1.155
V
V_{CCR_R}
Receiver power (right side)
1.045
1.1
1.155
V
V_{CCT_L}
Transmitter power (left side)
1.045
1.1
1.155
V
V_{CCT_R}
Transmitter power (right side)
1.045
1.1
1.155
V
V_{CCL_GXBLn} ⁽³⁾
Transceiver clock power (left side)
1.05
1.1
1.15
V
V_{CCL_GXBRn} ⁽³⁾
Transceiver clock power (right side)
1.05
1.1
1.15
V
V_{CCH_GXBLn} ⁽³⁾
V_{CCH_GXBRn} ⁽³⁾
Transmitter output buffer power (left side)
Transmitter output buffer power (right side)
1.33/1.425 1.4/1.5 ⁽⁴⁾ 1.47/1.575 V
Notes to Table 1–7:
(1) Transceiver power supplies do not have power-on-reset (POR) circuitry. After initial power-up, violating the transceiver power supply operating
conditions could lead to unpredictable link behavior.
(2) V_{CCA_L/R} must be connected to a 3.0-V supply if the clock multiplier unit (CMU) phase-locked loop (PLL), receiver clock data recovery (CDR),
or both, are configured at a base data rate > 4.25 Gbps. For data rates up to 4.25 Gbps, you can connect V_{CCA_L/R} to either 3.0 V or 2.5 V.
(3) n = 0, 1, 2, or 3.
(4) V_{CCH_GXBL/R} must be connected to a 1.4-V supply if the transmitter channel data rate is > 6.5 Gbps. For data rates up to 6.5 Gbps, you can
connect V_{CCH_GXBL/R} to either 1.4 V or 1.5 V.
Table 1–8 lists the recommended operating conditions for the Stratix IV GT
transceiver power supply.
Table 1–8. Transceiver Power Supply Operating Conditions for Stratix IV GT Devices (Part 1 of 2) ⁽¹⁾, ⁽²⁾
Symbol
V_{CCA_L}
V_{CCA_R}
V_{CCHIP_L}
V_{CCHIP_R}
V_{CCR_L}
Description
Transceiver high voltage power (left side)
Transceiver high voltage power (right side)
Transceiver HIP digital power (left side)
Transceiver HIP digital power (right side)
Receiver power (left side)
Minimum
3.17
3.17
0.92
0.92
1.15
Typical
3.3
3.3
0.95
0.95
1.2
Maximum Unit
3.43
V
3.43
V
0.98
V
0.98
V
1.25
V
July 2012 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum