EP4SGX360KF40C3N Datasheet, PDF (33/82 Pages) Altera Corporation – This chapter covers the electrical and switching characteristics for Stratix IV devices

Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
1–25
Figure 1–1 shows the top-to-bottom AC gain curve for equalization settings 0 to 15.
Figure 1–1. AC Gain Curves for Equalization Settings 0 to 15 (Bottom to Top)
Table 1–24 lists the Stratix IV GT transceiver specifications.
Table 1–24. Transceiver Specifications for Stratix IV GT Devices (Part 1 of 8)
Symbol/
Description
–1 Industrial Speed –2 Industrial Speed –3 Industrial Speed
Conditions
Grade
Grade
Grade
Unit
Min Typ Max Min Typ Max Min Typ Max
Reference Clock
Supported I/O
Standards
Input frequency
from REFCLK input
pins
Phase frequency
detector (CMU PLL
and receiver CDR)
Absolute V_MAX for a
REFCLK pin
Operational V_MAX for
a REFCLK pin
Absolute V_MIN for a
REFCLK pin
1.2 V PCML, 1.4 V PCML, 1.5 V PCML, 2.5 V PCML, Differential LVPECL ⁽³⁾, LVDS
—
50 — 706.25 50 — 706.25 50 — 706.25
MHz
—
50 — 425 50 — 425 50 — 425
MHz
—
— — 1.6 — — 1.6 — — 1.6
V
—
— — 1.5 — — 1.5 — — 1.5
V
—
-0.3 — — -0.3 —
— -0.3 —
—
V
July 2012 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum