EP4SGX360KF40C3N Datasheet, PDF (58/82 Pages) Altera Corporation – This chapter covers the electrical and switching characteristics for Stratix IV devices

1–50
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
DSP Block Specifications
Table 1–35 lists the Stratix IV DSP block performance specifications.
Table 1–35. Block Performance Specifications for Stratix IV DSP Devices ⁽¹⁾
Resources
Used
Performance
Mode
Number of
Multipliers
–1 Industrial
and–2/–2×
Commercial/
Industrial
Speed Grade
–3
–3
–4
–4
Commercial Industrial Commercial Industrial
Speed
Speed
Speed
Speed
Grade
Grade
Grade
Grade
Unit
9×9-bit multiplier (A, C, E, G) ⁽²⁾
1
9×9-bit multiplier (B, D, F, H) ⁽²⁾
1
12×12-bit multiplier (A, E) ⁽³⁾
1
12×12-bit multiplier (B, D, F, H) ⁽³⁾
1
520
460
460
400
400 MHz
520
460
460
400
400 MHz
540
500
500
440
440 MHz
540
500
500
440
430 MHz
18×18-bit multiplier
1
600
550
550
480
480 MHz
36×36-bit multiplier
1
480
440
440
380
380 MHz
18×18-bit multiply accumulator
4
490
440
440
380
380 MHz
18×18-bit multiply adder
4
510
470
470
410
400 MHz
18×18-bit multiply adder-signed full
precision
2
490
450
440
390
390 MHz
18×18-bit multiply adder with
loopback ⁽⁴⁾
2
390
350
350
310
300 MHz
36-bit shift (32-bit data)
1
490
440
440
380
380 MHz
Double mode
1
480
440
440
380
370 MHz
Notes to Table 1–35:
(1) Maximum is for fully pipelined block with Round and Saturation disabled.
(2) The DSP block implements eight independent 9b´9b multiplies using A, B, C, D for the top DSP half block and E, F, G, H for the bottom DSP half block
multipliers.
(3) The DSP block implements six independent 12b´12b multiplies using A, B, D for the top DSP half block and E, F, H for the bottom DSP half block
multipliers.
(4) Maximum for loopback input registers disabled, Round and Saturation disabled, and pipeline and output registers enabled.
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
July 2012 Altera Corporation