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EP4SGX360KF40C3N Datasheet, PDF (24/82 Pages) Altera Corporation – This chapter covers the electrical and switching characteristics for Stratix IV devices | |||
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Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
1â16
Transceiver Performance Specifications
This section describes transceiver performance specifications.
Table 1â23 lists the Stratix IV GX transceiver specifications.
Table 1â23. Transceiver Specifications for Stratix IV GX Devices (Part 1 of 9)
Symbol/
Description
Conditions
â2 Commercial
Speed Grade
â3 Commercial/
Industrial and
â2Ã Commercial
Speed Grade (1)
â3 Military (2)
and â4
Commercial/Industrial
Speed Grade
Unit
Min Typ Max Min Typ Max Min Typ Max
Reference Clock
Supported I/O
Standards
Input frequency
from REFCLK input
pins
Phase frequency
detector (CMU PLL
and receiver CDR)
Absolute VMAX for a
REFCLK pin
Operational VMAX for
a REFCLK pin
Absolute VMIN for a
REFCLK pin
Rise/fall time (21)
Duty cycle
Peak-to-peak
differential input
voltage
Spread-spectrum
modulating clock
frequency
Spread-spectrum
downspread
On-chip termination
resistors
VICM (AC coupled)
VICM (DC coupled)
1.2 V PCML, 1.4 V PCML 1.5 V PCML, 2.5 V PCML, Differential LVPECL (4), LVDS, HCSL
â
50 â 697 50 â 697 50 â 637.5 MHz
â
50 â 425 50 â 325 50 â 325 MHz
â
â â 1.6 â â 1.6 â â 1.6
V
â
â â 1.5 â â 1.5 â â 1.5
V
â
-0.4 â â -0.4 â â -0.4 â â
V
â
â â 0.2 â
â 0.2 â â 0.2
UI
â
45 â 55 45 â 55 45 â
55
%
â
200 â 1600 200 â 1600 200 â 1600 mV
PCIe
30 â 33 30 â 33 30 â 33 kHz
0 to
0 to
0 to
PCIe
â
ââ
ââ
â
â
-0.5%
-0.5%
-0.5%
â
â 100 â â 100 â â 100 â
ï
â
1100 ± 10%
1100 ± 10%
1100 ± 10%
mV
HCSL I/O
standard for
PCIe reference
250
â
550 250
â
550 250
â
550
mV
clock
July 2012 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
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