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EP4SGX360KF40C3N Datasheet, PDF (55/82 Pages) Altera Corporation – This chapter covers the electrical and switching characteristics for Stratix IV devices | |||
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Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
1â47
Transceiver Datapath PCS Latency
f For more information about:
â Basic mode PCS latency, refer to Figure 1-90 through Figure 1-97 in the Transceiver
Architecture in Stratix IV Devices chapter.
â PCIe mode PCS latency, refer to Figure 1-102 in the Transceiver Architecture in
Stratix IV Devices chapter.
â XAUI mode PCS latency, refer to Figure 1-119 in the Transceiver Architecture in
Stratix IV Devices chapter.
â GIGE mode PCS latency, refer to Figure 1-128 in the Transceiver Architecture in
Stratix IV Devices chapter.
â SONET/SDH mode PCS latency, refer to Figure 1-136 in the Transceiver
Architecture in Stratix IV Devices chapter.
â SDI mode PCS latency, refer to Figure 1-141 in the Transceiver Architecture in Stratix
IV Devices chapter.
â (OIF) CEI PHY mode PCS latency, refer to Figure 1-143 in the Transceiver
Architecture in Stratix IV Devices chapter.
Core Performance Specifications
This section describes the clock tree, phase-locked loop (PLL), digital signal
processing (DSP), TriMatrix, configuration, JTAG, and chip-wide reset (Dev_CLRn)
specifications.
For the Stratix IV GT â1 and â2 speed grade specifications, refer to the â2/â2Ã speed
grade column. For the Stratix IV GT â3 speed grade specification, refer to the â3 speed
grade column, unless otherwise specified.
Clock Tree Specifications
Table 1â33 lists the clock tree specifications for Stratix IV devices.
Table 1â33. Clock Tree Performance for Stratix IV Devices
Symbol
Performance
Unit
â2/â2Ã Speed Grade â3 Speed Grade â4 Speed Grade
Global clock and
Regional clock
800
700
500
MHz
Periphery clock
550
500
500
MHz
July 2012 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
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