EP3C5M164I7N Datasheet, PDF (45/274 Pages) Altera Corporation – Cyclone III Device Handbook

Chapter 3: Memory Blocks in the Cyclone III Device Family
Memory Modes
3–11
True Dual-Port Mode
True dual-port mode supports any combination of two-port operations: two reads,
two writes, or one read and one write, at two different clock frequencies. Figure 3–11
shows the Cyclone III device family true dual-port memory configuration.
Figure 3–11. Cyclone III Device Family True Dual-Port Memory ⁽¹⁾
data_a[ ]
address_a[ ]
wren_a
byteena_a[]
addressstall_a
clock_a
clocken_a
rden_a
aclr_a
q_a[]
data_b[ ]
address_b[]
wren_b
byteena_b[]
addressstall_b
clock_b
clocken_b
rden_b
aclr_b
q_b[]
Note to Figure 3–11:
(1) True dual-port memory supports input or output clock mode in addition to the independent clock mode shown.
1 The widest bit configuration of the M9K blocks in true dual-port mode is 512 × 16-bit
(18-bit with parity).
Table 3–4 lists the possible M9K block mixed-port width configurations.
Table 3–4. Cyclone III Device Family M9K Block Mixed-Width Configurations (True Dual-Port
Mode)
Read Port
8192 × 1
4096 × 2
2048 × 4
1024 × 8
512 × 16
1024 × 9
512 × 18
8192 × 1
v
v
v
v
v
—
—
4096 × 2
v
v
v
v
v
—
—
Write Port
2048 × 4
v
v
v
v
v
—
—
1024 × 8
v
v
v
v
v
—
—
512 × 16
v
v
v
v
v
—
—
1024 × 9
—
—
—
—
—
v
v
512 × 18
—
—
—
—
—
v
v
In true dual-port mode, M9K memory blocks support separate wren and rden signals.
You can save power by keeping the rden signal low (inactive) when not reading.
Read-during-write operations to the same address can either output “New Data” at
that location or “Old Data”. To choose the desired behavior, set the Read-During-
Write option to either New Data or Old Data in the RAM MegaWizard Plug-In
Manager in the Quartus II software. For more information about this behavior, refer to
“Read-During-Write Operations” on page 3–15.
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1