EP3C5M164I7N Datasheet, PDF (153/274 Pages) Altera Corporation – Cyclone III Device Handbook

Chapter 8: External Memory Interfaces in the Cyclone III Device Family
Cyclone III Device Family Memory Interfaces Features
8–11
Cyclone III Device Family Memory Interfaces Features
This section describes Cyclone III device family memory interfaces, including DDR
input registers, DDR output registers, OCT, and phase-lock loops (PLLs).
DDR Input Registers
The DDR input registers are implemented with three internal logic element (LE)
registers for every DQ pin. These LE registers are located in the logic array block (LAB)
adjacent to the DDR input pin.
Figure 8–4 shows Cyclone III device family DDR input registers.
Figure 8–4. Cyclone III Device Family DDR Input Registers
DDR Input Registers in Cyclone III Device Family
dataout_h
dataout_l
LE
Register
Register C_I
LE
Register
Input Register A_I
neg_reg_out
LE
Register
Input Register B_I
DQ
Capture Clock
PLL
The DDR data is first fed to two registers, input register A_I and input register B_I.
■ Input register A_I captures the DDR data present during the rising edge of the clock
■ Input register B_I captures the DDR data present during the falling edge of the clock
■ Register C_I aligns the data before it is synchronized with the system clock
The data from the DDR input register is fed to two registers, sync_reg_h and
sync_reg_l, then the data is typically transferred to a FIFO block to synchronize the
two data streams to the rising edge of the system clock. Because the read-capture
clock is generated by the PLL, the read-data strobe signal (DQS or CQ) is not used
during read operation in Cyclone III device family; hence, postamble is not a concern
in this case.
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1