EP3C5M164I7N Datasheet, PDF (190/274 Pages) Altera Corporation – Cyclone III Device Handbook

9–32
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
Figure 9–12 shows the recommended balanced star routing for multiple bus master
interfaces to minimize signal integrity issue.
Figure 9–12. Balanced Star Routing
DCLK
Cyclone III
Master Device
M (1)
External
Master Device
N (2)
N (2)
Micron Flash
Notes to Figure 9–12:
(1) Altera does not recommend M to exceed six inches as listed in Table 9–12 on page 9–30.
(2) Altera recommends using a balanced star routing. Try to keep the N length equal and as short as possible to minimize
reflection noise from the transmission line. The M length is applicable for this setup.
Estimating the AP Configuration Time
AP configuration time is dominated by the time it takes to transfer data from the
parallel flash to the Cyclone III devices. This parallel interface is clocked by the
Cyclone III DCLK output (generated from an internal oscillator). As listed in Table 9–8
on page 9–14, the DCLK minimum frequency when using the 40-MHz oscillator is
20 MHz (50 ns). In word-wide cascade programming, the DATA[15..0] bus transfers a
16-bit word and essentially cuts configuration time to approximately 1/16 of the AS
configuration time. Therefore, the maximum configuration time estimation for an
EP3C40 device (9,600,000 bits of uncompressed data) is defined in Equation 9–4 and
Equation 9–5.
Equation 9–4.
Size  _^m---₁---_6a---^x-_b--ⁱ-_i-^m-_t--_s--^u--_p--^m--_e---_r-^D---_D--^C--_C--^L--_L--^K--_K----^p--_c-^e--_y-^r--_c-ⁱ-^o-_l-_e--^d--_ = estimated maximum configuration ti
Equation 9–5.
9,600,000
bits



1^--5-6^--0---b^--n-i^--ts^--s^{-}
=
30 ms
To estimate a typical configuration time, use the typical DCLK period listed in Table 9–8
on page 9–14. With a typical DCLK period of 33.33 ns, the typical configuration time is
20 ms.
Cyclone III Device Handbook
Volume 1
August 2012 Altera Corporation