EP3C5M164I7N Datasheet, PDF (144/274 Pages) Altera Corporation – Cyclone III Device Handbook

8–2
Chapter 8: External Memory Interfaces in the Cyclone III Device Family
Cyclone III Device Family Memory Interfaces Pin Support
Figure 8–1 shows the block diagram of a typical external memory interface data path
in Cyclone III device family.
Figure 8–1. Cyclone III Device Family External Memory Data Path ⁽¹⁾
DQS/CQ/CQn
DQ
OE
IOE
Register
OE
IOE
Register
IOE
Register
VCC
IOE
Register
IOE
Register
DataA
IOE
Register
LE
Register
GND
IOE
Register
System Clock
PLL
-90° Shifted Clock
Capture Clock
Note to Figure 8–1:
(1) All clocks shown here are global clocks.
DataB
IOE
Register
LE
Register
LE
Register
Cyclone III Device Family Memory Interfaces Pin Support
Cyclone III device family uses data (DQ), data strobe (DQS), clock, command, and
address pins to interface with external memory. Some memory interfaces use the data
mask (DM) or byte write select (BWS#) pins to enable data masking. This section
describes how Cyclone III device family supports all these different pins.
Data and Data Clock/Strobe Pins
Cyclone III device family data pins for external memory interfaces are called D for
write data, Q for read data, or DQ for shared read and write data pins. The read-data
strobes or read clocks are called DQS pins. Cyclone III device family supports both
bidirectional data strobes and unidirectional read clocks. Depending on the external
memory standard, the DQ and DQS are bidirectional signals (in DDR2 and
DDR SDRAM) or unidirectional signals (in QDR II SRAM). Connect the bidirectional
DQ data signals to the same Cyclone III device family DQ pins. For unidirectional D or Q
signals, connect the read-data signals to a group of DQ pins and the write-data signals
to a different group of DQ pins.
1 In QDR II SRAM, the Q read-data group must be placed at a different V_REF bank
location from the D write-data group, command, or address pins.
In Cyclone III device family, DQS is used only during write mode in DDR2 and
DDR SDRAM interfaces. Cyclone III device family ignores DQS as the read-data strobe
because the PHY internally generates the read capture clock for read mode. However,
you must connect the DQS pin to the DQS signal in DDR2 and DDR SDRAM interfaces,
or to the CQ signal in QDR II SRAM interfaces.
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation