EP3C5M164I7N Datasheet, PDF (134/274 Pages) Altera Corporation – Cyclone III Device Handbook

7–12
Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
High-Speed I/O Standards Support
Figure 7–7 shows the RSDS interface with a single resistor network on the top and
bottom I/O banks.
Figure 7–7. RSDS Interface with Single Resistor Network on the Top and Bottom I/O Banks
Cyclone III Device Family
Emulated
RSDS Transmitter
Single Resistor Network
RSDS Receiver
50 Ω
R_P
100 Ω
50 Ω
Note to Figure 7–7:
(1) R_P = 100 
LVPECL I/O Support in the Cyclone III Device Family
The LVPECL I/O standard is a differential interface standard that requires a 2.5-V
V_CCIO. This standard is used in applications involving video graphics,
telecommunications, data communications, and clock distribution. The Cyclone III
device family supports the LVPECL input standard at the dedicated clock input pins
only. The LVPECL receiver requires an external 100- termination resistor between
the two signals at the input buffer.
f For more information about the LVPECL I/O standard electrical specification, refer to
the Cyclone III Device Data Sheet and Cyclone III LS Device Data Sheet chapters.
AC coupling is required when the LVPECL common mode voltage of the output
buffer is higher than the Cyclone III device family LVPECL input common mode
voltage.
Figure 7–8 shows the AC-coupled termination scheme. The 50- resistors used at the
receiver are external to the device. DC-coupled LVPECL is supported if the LVPECL
output common mode voltage is in the Cyclone III device family LVPECL input buffer
specification (Figure 7–9).
Figure 7–8. LVPECL AC-Coupled Termination
LVPECL
Transmitter
0.1 µF
0.1 µF
Z0 = 50 
VICM
Z0 = 50 
Cyclone III Device Family
LVPECL Receiver
50 
50 
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation