EP3C5M164I7N Datasheet, PDF (249/274 Pages) Altera Corporation – Cyclone III Device Handbook

Chapter 10: Hot-Socketing and Power-On Reset in the Cyclone III Device Family
Hot-Socketing Feature Implementation
10–3
Hot-Socketing Feature Implementation
Each I/O pin has the circuitry shown in Figure 10–1. The hot-socketing circuit does
not include CONF_DONE, nCEO, and nSTATUS pins to ensure that they are able to operate
during configuration. Thus, it is expected behavior for these pins to drive out during
power up and power down sequences.
Figure 10–1 shows the hot-socketing circuit block diagram for Cyclone III device
family.
Figure 10–1. Hot-socketing Circuit Block Diagram for Cyclone III Device Family
V_CCIO
Power On
Reset
Monitor
Weak
R
Pull-Up
Resistor
PAD
Output Enable
Voltage
Tolerance
Control
Hot Socket
Output
Pre-Driver
Input Buffer
to Logic Array
The POR circuit monitors the voltage level of power supplies and keeps the I/O pins
tristated until the device is in user mode. The weak pull-up resistor (R) in Cyclone III
device family I/O element (IOE) keeps the I/O pins from floating. The 3.3-V tolerance
control circuit permits the I/O pins to be driven by 3.3 V before V_CCIO, V_CC, and V_CCA
supplies are powered up, and it prevents the I/O pins from driving out when the
device is not in user mode.
1 Altera uses GND as reference for hot-socketing operation and I/O buffer designs. To
ensure proper operation, Altera recommends connecting the GND between boards
before connecting the power supplies. This prevents the GND on your board from
being pulled up inadvertently by a path to power through other components on your
board. A pulled up GND can otherwise cause an out-of-specification I/O voltage or
current condition with the Altera^® device.
POR Circuitry
Cyclone III device family contains POR circuitry to keep the device in a reset state
until the power supply voltage levels have stabilized during power up. During POR,
all user I/O pins are tristated until the V_CC reaches the recommended operating
levels. In addition, the POR circuitry also ensures the V_CCIO level of I/O banks 1, 6, 7,
and 8 that contains configuration pins reach an acceptable level before configuration
is triggered.
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1