EP3C5M164I7N Datasheet, PDF (204/274 Pages) Altera Corporation – Cyclone III Device Handbook

9–46
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
If a system has multiple devices that contain the same configuration data, tie all
device nCE inputs to GND and leave nCEO pins floating. All other configuration pins
(nCONFIG, nSTATUS, DCLK, DATA[7..0], and CONF_DONE) are connected to every device in
the chain. Configuration signals can require buffering to ensure signal integrity and
prevent clock skew problems. Ensure that the DCLK and DATA lines are buffered.
Devices must be of the same density and package. All devices start and complete
configuration at the same time.
Figure 9–22 shows multi-device FPP configuration when both Cyclone III device
family is receiving the same configuration data.
Figure 9–22. Multi-Device FPP Configuration Using an External Host When Both Devices Receive
the Same Data
Memory
VCCIO (1) VCCIO (1)
ADDR DATA[7..0]
10 k 10 k
External Host
(MAX II Device or
Microprocessor)
GND
Cyclone III Device Family 1
Cyclone III Device Family 2
(3)
MSEL[3..0]
CONF_DONE
nSTATUS
nCE
nCEO
N.C. (2)
DATA[7..0] (4)
nCONFIG
DCLK (4)
GND
MSEL[3..0]
(3)
CONF_DONE
nSTATUS
nCE
nCEO N.C. (2)
DATA[7..0] (4)
nCONFIG
DCLK (4)
Buffers (4)
Notes to Figure 9–22:
(1) The pull-up resistor must be connected to a supply that provides an acceptable input signal for all devices in the
chain. V_CC must be high enough to meet the V_IH specification of the I/O on the device and the external host.
(2) The nCEO pins of both devices are left unconnected or used as user I/O pins when configuring the same configuration
data into multiple devices.
(3) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect MSEL[3..0],
refer to Table 9–7 on page 9–11. Connect the MSEL pins directly to V_CCA or GND.
(4) All I/O inputs must maintain a maximum AC voltage of 4.1 V. DATA[7..0] and DCLK must fit the maximum overshoot
equation outlined in “Configuration and JTAG Pin I/O Requirements” on page 9–7.
You can use a single configuration chain to configure Cyclone III device family with
other Altera devices that support the FPP configuration. To ensure that all devices in
the chain complete configuration at the same time or that an error flagged by one
device starts reconfiguration in all devices, tie all the device CONF_DONE and nSTATUS
pins together.
f For more information about configuring multiple Altera devices in the same
configuration chain, refer to the Configuring Mixed Altera FPGA Chains chapter in
volume 2 of the Configuration Handbook.
Cyclone III Device Handbook
Volume 1
August 2012 Altera Corporation