|
EP3C5M164I7N Datasheet, PDF (14/274 Pages) Altera Corporation – Cyclone III Device Handbook | |||
|
◁ |
1â2
Chapter 1: Cyclone III Device Family Overview
Cyclone III Device Family Features
Design Security Feature
Cyclone III LS devices offer the following design security features:
â Configuration security using advanced encryption standard (AES) with 256-bit
volatile key
â Routing architecture optimized for design separation flow with the Quartus® II
software
â Design separation flow achieves both physical and functional isolation
between design partitions
â Ability to disable external JTAG port
â Error Detection (ED) Cycle Indicator to core
â Provides a pass or fail indicator at every ED cycle
â Provides visibility over intentional or unintentional change of configuration
random access memory (CRAM) bits
â Ability to perform zeroization to clear contents of the FPGA logic, CRAM,
embedded memory, and AES key
â Internal oscillator enables system monitor and health check capabilities
Increased System Integration
â High memory-to-logic and multiplier-to-logic ratio
â High I/O count, low-and mid-range density devices for user I/O constrained
applications
â Adjustable I/O slew rates to improve signal integrity
â Supports I/O standards such as LVTTL, LVCMOS, SSTL, HSTL, PCI, PCI-X,
LVPECL, bus LVDS (BLVDS), LVDS, mini-LVDS, RSDS, and PPDS
â Supports the multi-value on-chip termination (OCT) calibration feature to
eliminate variations over process, voltage, and temperature (PVT)
â Four phase-locked loops (PLLs) per device provide robust clock management and
synthesis for device clock management, external system clock management, and
I/O interfaces
â Five outputs per PLL
â Cascadable to save I/Os, ease PCB routing, and reduce jitter
â Dynamically reconfigurable to change phase shift, frequency multiplication or
division, or both, and input frequency in the system without reconfiguring the
device
â Remote system upgrade without the aid of an external controller
â Dedicated cyclical redundancy code checker circuitry to detect single-event upset
(SEU) issues
â Nios® II embedded processor for Cyclone III device family, offering low cost and
custom-fit embedded processing solutions
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
|
▷ |